SLOSEB7A September   2024  – October 2024 LOG300

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics Low Noise Amplifier (LNA) 
    6. 5.6 Electrical Characteristics Log Detector
    7. 5.7 Electrical Characteristics LNA + Log Detector (AFE)
    8. 5.8 Typical Characteristics: VCC = 5V
    9. 5.9 Typical Characteristics: VCC = 3.3V
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Offset Correction Loop (OCL)
      2. 7.3.2 Single and Differential Input
      3. 7.3.3 Input Frequency Detect
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Ultrasonic Distance Measurement
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGT|16
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

Figure 4-1 D Package, 16-Pin SOIC (top view)
Figure 4-2 RGT Package, 16-Pin VQFN (top view)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
D (SOIC) RGT (VQFN)
AFE_En 1 14 I LNA and Log Detector block enable and disable pin. AFE_En = High for AFE enable. Floating this pin keeps both blocks enabled as well.
AGND 13 10 P Analog ground for LNA and Log detector block
Buffer 10 7 O Noninverting buffered output. VBuffer = VLog_Out × 2.
DGND 2 15 P Digital ground for Freq_Out pin
Freq_Out 8 5 O This pin toggles at the same signal frequency applied at the Log_In.
Freq_Supply 7 4 P Power supply for Freq_Out function. Float this pin if the frequency-detection feature is not required.
Inv_Buffer 9 6 O Inverted buffered output. VInv_Buffer = VLog_Out × –2.
LNA_En 3 16 I Low-noise amplifier enable and disable. LNA_En = High for LNA enable. Floating this pin keeps the LNA enabled as well.
LNA_In 16 13 I Low-noise amplifier input
LNA_Out 14 11 O Low-noise amplifier output
Log_Inm 11 8 I Inverting input of Log Detector block. Connect an appropriate capacitor to ground when used in a single-ended input. Refer to Section 7.3.2.
Log_Inp 12 9 I Noninverting input of Log Detector block
Log_Out 5 2 O Unbuffered output of Log Detector block. Connect an appropriate resistor RF (to set the input to output slope) and capacitor CF (to set the response time).
Offset_Cap 15 12 I Connect a recommended capacitor from this pin to ground. This capacitor sets the pole of the internal offset correction loop. Refer to Section 7.3.1 for the recommended capacitor.
Ref_Res 6 3 I Connect a 1% 56kΩ resistor to this pin. Float this pin if the default relaxed slope accuracy is acceptable.
VCC 4 1 P Supply
Thermal Pad

—

 Thermal Pad P Thermal pad. Electrically isolated from the device. Connect to a heat spreading plane, typically ground.
(1) I = input, O = output, I/O = input or output, G = ground, P = power.