JAJSPI9H June   2011  – November 2024 LP2951-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics (Both Legacy and New Chip)
    6. 5.6 Timing Requirements (New Chip only)
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Reverse Current
      2. 7.1.2 Input and Output Capacitor Requirements
      3. 7.1.3 Estimating Junction Temperature
      4. 7.1.4 Power Dissipation (PD)
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Recommended Capacitor Types
          1. 7.2.1.1.1 Recommended Capacitors (Legacy Chip)
            1. 7.2.1.1.1.1 ESR Range (Legacy Chip)
          2. 7.2.1.1.2 Recommended Capacitors (New Chip)
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Feedback Resistor Selection
        2. 7.2.2.2 Feedforward Capacitor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

LP2951-Q1 D Package (LP2951-50-Q1),8-Pin SOIC(Top View)Figure 4-1 D Package (LP2951-50-Q1),8-Pin SOIC(Top View)
LP2951-Q1 DRG Package,8-Pin WSON With Exposed Thermal Pad(Top View)Figure 4-2 DRG Package,8-Pin WSON With Exposed Thermal Pad(Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
ERROR 5 O Active-low, open-drain error output. Goes low when VOUT drops by 6% of the nominal value.
FEEDBACK 7 I Determines the output voltage. Connect to VTAP (with OUTPUT tied to SENSE) for fixed output option, or connect to a resistor divider for adjustable output option.
GND 4 — Ground
INPUT 8 I Input supply pin. Use a capacitor with a value of 1µF or larger from this pin to ground is recommended. See the Input and Output Capacitor Requirements section for more information.
OUTPUT 1 O

A capacitor is required from OUTPUT to GND for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUTPUT to GND(2). Place the output capacitor as close to the device output as possible. See the Input and Output Capacitor Requirements section for more details.
SENSE 2 I Senses the output voltage. Connect to OUTPUT (with FEEDBACK tied to VTAP) for fixed output option only. If using the device as adjustable output, this pin must be left floating.
SHUTDOWN 3 I Active-high input. A high signal disables the device; a low signal enables the device.
VTAP 6 O Connect to FEEDBACK for fixed output option. If using the device as adjustable output, this pin must be left floating.
(1) I = Input, O = Output.
(2) The nominal output capacitance must be greater than 1μF. Throughout this document, the nominal derating on these capacitors is assumed to be 50%. Verify that the effective capacitance at the pin is greater than 1μF.