JAJSPI9H
June 2011 – November 2024
LP2951-Q1
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics (Both Legacy and New Chip)
5.6
Timing Requirements (New Chip only)
5.7
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Output Enable
6.3.2
Dropout Voltage
6.3.3
Current Limit
6.3.4
Undervoltage Lockout (UVLO)
6.3.5
Thermal Shutdown
6.4
Device Functional Modes
6.4.1
Shutdown Mode
7
Application and Implementation
7.1
Application Information
7.1.1
Reverse Current
7.1.2
Input and Output Capacitor Requirements
7.1.3
Estimating Junction Temperature
7.1.4
Power Dissipation (PD)
7.2
Typical Application
7.2.1
Design Requirements
7.2.1.1
Recommended Capacitor Types
7.2.1.1.1
Recommended Capacitors (Legacy Chip)
7.2.1.1.1.1
ESR Range (Legacy Chip)
7.2.1.1.2
Recommended Capacitors (New Chip)
7.2.2
Detailed Design Procedure
7.2.2.1
Feedback Resistor Selection
7.2.2.2
Feedforward Capacitor
7.2.3
Application Curves
7.3
Power Supply Recommendations
7.4
Layout
7.4.1
Layout Guidelines
7.4.2
Layout Example
8
Device and Documentation Support
8.1
Device Support
8.1.1
Development Support
8.1.2
Device Nomenclature
8.2
Documentation Support
8.2.1
Related Documentation
8.3
ドキュメントの更新通知を受け取る方法
8.4
サポート・リソース
8.5
Trademarks
8.6
静電気放電に関する注意事項
8.7
用語集
9
Revision History
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
D|8
MSOI002K
DRG|8
MPDS151B
サーマルパッド・メカニカル・データ
DRG|8
QFND128G
発注情報
jajspi9h_oa
jajspi9h_pm
7.4.2
Layout Example
Figure 7-14
Layout Example (D Package)