JAJSQK8F april   2000  – july 2023 LP2980-ADJ

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable
      2. 7.3.2 Dropout Voltage
      3. 7.3.3 Current Limit
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Output Pulldown
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Feedback Resistors
      2. 8.1.2 Recommended Capacitor Types
        1. 8.1.2.1 Recommended Capacitors for the New Chip
        2. 8.1.2.2 Recommended Capacitors for the Legacy Chip
      3. 8.1.3 Input and Output Capacitor Requirements
      4. 8.1.4 Feed-Forward Capacitor (CFF)
      5. 8.1.5 Reverse Current
      6. 8.1.6 Power Dissipation (PD)
      7. 8.1.7 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting VOUT For the LP2980-ADJ LDO
        2. 8.2.2.2 ON/OFF Input Operation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.1 External Feedback Resistors

The output voltage is set using the ADJ pin with help of the external feedback resistors, R1 and R2 (see Figure 8-2), according to the following equation:

Equation 2. V O U T   =   V A D J   ×   ( 1   +   R 1   /   R 2 )

For the legacy chip, use a resistor from the ADJ pin to ground with a value of 51.1 kΩ.

For the new chip, to ignore the ADJ pin current error term in the VOUT equation, set the feedback divider current to 100 times the ADJ pin current listed in the Electrical CharacteristicsElectrical CharacteristicsElectrical CharacteristicsElectrical CharacteristicsElectrical CharacteristicsElectrical Characteristics table. This setting provides the maximum feedback divider series resistance, as shown in the following equation:

Equation 3. R 1   +   R 2   ≤   V O U T   /   ( I A D J   ×   100 )