JAJS850O March   2000  – December 2023 LP2981-N

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Thermal Shutdown
      6. 6.3.6 Output Pulldown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Recommended Capacitor Types
        1. 7.1.1.1 Recommended Capacitors for the Legacy Chip
        2. 7.1.1.2 Recommended Capacitors for the New Chip
      2. 7.1.2 Input and Output Capacitor Requirements
      3. 7.1.3 Estimating Junction Temperature
      4. 7.1.4 Power Dissipation (PD)
      5. 7.1.5 Reverse Current
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 ON and OFF Input Operation
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 サード・パーティ製品に関する免責事項
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Related Documentation
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

GUID-20231125-SS0I-S5RS-GZWS-GFCWQBB7K2CD-low.svg Figure 4-1 DBV Package,5-Pin SOT-23(Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
1 IN I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See the Section 7.1.2 section for more information.
2 GND — Common ground (device substrate).
3 ON/OFF I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the Section 5.5 table. Tie this pin to VIN if unused.
4 NC — For new chip: Not internally connected. This pin can be left open or tied to ground for improved thermal performance.

For legacy chip: DO NOT CONNECT. Device pin 4 is reserved for post packaging test and calibration of the LP2981-N VOUT accuracy. Device pin 4 must be left floating. Do not connect to any potential. Do not connect to ground. Any attempt to do pin continuity testing on device pin 4 is discouraged. Continuity test results will be variable depending on the actions of the factory calibration. Aggressive pin continuity testing (high voltage, or high current) on device pin 4 can activate the trim circuitry forcing VOUT to move out of tolerance.
5 OUT O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground. See the Section 7.1.2 section for more information.