SNOSCY7 June   2014 LP2996A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin Descriptions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Capacitor
      2. 8.1.2 Output Capacitor
      3. 8.1.3 Thermal Dissipation
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application Circuit
      2. 8.2.2 DDR-III Applications
      3. 8.2.3 DDR-II Applications
      4. 8.2.4 SSTL-2 Applications
      5. 8.2.5 Level Shifting
        1. 8.2.5.1 Output Capacitor Selection
      6. 8.2.6 HSTL Applications
      7. 8.2.7 QDR Applications
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
    4. 10.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • 1.35V Minimum VDDQ
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown
  • LP2998/8Q recommended for -40°C to 125°C

2 Applications

  • DDR1, DDR2, DDR3, and DDR3L Termination Voltage
  • FPGA
  • Industrial/Medical PC
  • SSTL-2 and SSTL-3 Termination
  • HSTL Termination

3 Description

The LP2996A linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, DDR3 and DDR3L VTT bus termination with VDDQ min of 1.35V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2996A also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2996A is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LP2996A SO PowerPAD (8) 4.89 mm x 3.90 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

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4 Revision History

DATE REVISION NOTES
June 2014 * Initial release.