SNOSCY7 June   2014 LP2996A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin Descriptions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Capacitor
      2. 8.1.2 Output Capacitor
      3. 8.1.3 Thermal Dissipation
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application Circuit
      2. 8.2.2 DDR-III Applications
      3. 8.2.3 DDR-II Applications
      4. 8.2.4 SSTL-2 Applications
      5. 8.2.5 Level Shifting
        1. 8.2.5.1 Output Capacitor Selection
      6. 8.2.6 HSTL Applications
      7. 8.2.7 QDR Applications
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
    4. 10.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Detailed Description

7.1 Overview

The LP2996A linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, DDR3 and DDR3L VTT bus termination with VDDQ min of 1.35V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination.

7.2 Functional Block Diagram

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7.3 Feature Description

The LP2996A is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2. The output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The output stage has been designed to maintain excellent load regulation while preventing shoot through. The LP2996A also incorporates two distinct power rails that separates the analog circuitry from the power output stage. This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits the LP2996A to provide a termination solution for DDR2-SDRAM, DDR3-SDRAM and DDR3L-SDRAM memory. For wide temperature designs, the LP2998/8Q is recommended for all DDR applications.

7.4 Device Functional Modes

The LP2996A can also be used to provide a termination voltage for other logic schemes such as SSTL-3 or HSTL. Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class II single parallel termination. This involves one RS series resistor from the chipset to the memory and one RT termination resistor. Typical values for RS and RT are 25 Ω, although these can be changed to scale the current requirements from the LP2996A. This implementation can be seen below in Figure 16.

20057506.gifFigure 16. SSTL-Termination Scheme