SNOSCY7 June   2014 LP2996A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin Descriptions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Capacitor
      2. 8.1.2 Output Capacitor
      3. 8.1.3 Thermal Dissipation
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application Circuit
      2. 8.2.2 DDR-III Applications
      3. 8.2.3 DDR-II Applications
      4. 8.2.4 SSTL-2 Applications
      5. 8.2.5 Level Shifting
        1. 8.2.5.1 Output Capacitor Selection
      6. 8.2.6 HSTL Applications
      7. 8.2.7 QDR Applications
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
    4. 10.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

  1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin.
  2. VSENSE should be connected to the VTT termination bus at the point where regulation is required. For motherboard applications an ideal location would be at the center of the termination bus.
  3. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the most accurate point for creating the reference voltage.
  4. For improved thermal performance excessive top side copper should be used to dissipate heat from the package. Numerous vias from the ground connection to the internal ground plane will help. Additionally these can be located underneath the package if manufacturing standards permit.
  5. Care should be taken when routing the VSENSE trace to avoid noise pickup from switching I/O signals. A 0.1uF ceramic capacitor located close to the SENSE can also be used to filter any unwanted high frequency signal. This can be an issue especially if long SENSE traces are used.
  6. VREF should be bypassed with a 0.01 µF or 0.1 µF ceramic capacitor for improved performance. This capacitor should be located as close as possible to the VREF pin.

10.2 Layout Examples

The LP2996A layout is very similar to the LP2998/Q layout. This is because the main difference between the two IC's is the wider temperature range, -40°C to 125°C, which the LP2998/Q offers. As such, the below example shows the layout from a LP2998EVM. These layout examples can be used to evaluate the LP2996A.

layout_01_snoscy7.pngFigure 29. LP2998EVM SO PowerPAD Layout Example (Front)
layout_02_snoscy7.pngFigure 30. LP2998EVM SO PowerPAD Layout Example (Back)