JAJSI22B July   2019  – November 2019 LP3470A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      基本的な動作回路
      2.      LP3470A の標準的な消費電流
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 RESET Time-Out Period
      2. 8.3.2 RESET Output
      3. 8.3.3 Pull-up Resistor Selection
      4. 8.3.4 VCC Transient Immunity
    4. 8.4 Device Functional Modes
      1. 8.4.1 RESET Output Low
      2. 8.4.2 RESET Output High
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 サポート・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

DBV Package
5-Pin SOT-23
Top View
LP3470A fig2-pinout-lp3470.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 SRT I Set reset time-out. Connect a capacitor between this pin and ground to select the reset time-out period (tD). tD = 619 × C1 (CSRT in µF and tD in ms). If no capacitor is connected, leave this pin floating.
2 GND — Ground pin.
3 VCC1 I Can be connected to VCC or left floating. DO NOT CONNECT TO GND.
4 VCC I Supply voltage, and reset threshold monitor input.
5 RESET O Open-drain, active-low reset output. Connect to an external pullup resistor. RESET changes from high to low whenever the monitored voltage (VCC) drops below the reset threshold voltage (VIT-). Once VCC exceeds the reset threshold (VIT-) + hysteresis (VHYS), RESET remains low for the reset time-out period (tD) and then deasserts to logic high.