The LP38690 and LP38692 low-dropout CMOS linear regulators provide tight output tolerance (2.5% typical), extremely low dropout voltage (450 mV at a 1-A load current, VOUT = 5 V), and excellent AC performance utilizing ultra low ESR ceramic output capacitors.
The low thermal resistance of the WSON, SOT-223, and TO-252 packages allow the full operating current to be used even in high ambient temperature environments.
The use of a PMOS power transistor means that no DC base drive current is required to bias it allowing ground pin current to remain below 100 µA regardless of load current, input voltage, or operating temperature.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LP38690 | TO-252 (3) | 6.58 mm x 6.10 mm |
WSON (6) | 3.00 mm x 3.00 mm | |
LP38692 | SOT-223 (5) | 6.50 mm x 3.56 mm |
WSON (6) | 3.00 mm x 3.00 mm |
Changes from L Revision (March 2015) to M Revision
Changes from K Revision (December 2014) to L Revision
Changes from J Revision (April 2013) to K Revision
Changes from I Revision (April 2013) to J Revision
PIN | TYPE | DESCRIPTION | ||||
---|---|---|---|---|---|---|
NAME | LP38690 | LP38692 | ||||
TO-252 | WSON | SOT-223 | WSON | |||
EN | — | — | 1 | 3 | I | The Enable (EN) pin allows the part to be turned ON and OFF by pulling this pin HIGH or LOW. |
GND | TAB | 2 | 5 | 2 | — | Circuit ground for the regulator. For the TO-252 and SOT-223 packages this is thermally connected to the die and functions as a heat sink when soldered down to a large copper plane. |
IN | 3 | 1, 6 | 4 | 1, 6 | I | This is the input supply voltage to the regulator. For WSON devices, both IN pins must be tied together for full current operation (500 mA maximum per pin). |
OUT | 1 | 4 | 3 | 4 | O | Regulated output voltage. |
SNS | — | 5 | — | 5 | I | WSON only - Output sense pin allows remote sensing at the load which eliminates the error in output voltage due to voltage drops caused by the resistance in the traces between the regulator and the load. This pin must be tied to VOUT. |
DAP | — | X | — | X | — | WSON only - The DAP (Exposed Pad) functions as a thermal connection when soldered to a copper plane. See WSON Mounting section in Layout for more information. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
V(max) All pins (with respect to GND) | –0.3 | 12 | V | |
IOUT(3) | Internally limited | |||
Junction temperature | −40 | 150 | °C | |
Lead temperature (soldering, 5 seconds) | 260 | |||
Power dissipation(2) | Internally limited | |||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN supply voltage | 2.7 | 10 | V | ||
Operating junction temperature | −40 | 125 | °C |
THERMAL METRIC(1) | LP38690 | LP38690/92 | LP38692 | UNIT | |
---|---|---|---|---|---|
TO-252 | WSON | SOT-223 | |||
3 PINS | 6 PINS | 5 PINS | |||
RθJA(2) | Junction-to-ambient thermal resistance | 50.5 | 50.6 | 68.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 52.6 | 44.4 | 52.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 29.7 | 24.9 | 13.0 | °C/W |
ψJT | Junction-to-top characterization parameter | 4.8 | 0.4 | 5.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 29.3 | 25.1 | 12.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.5 | 5.4 | n/a | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOUT | Output voltage tolerance | –2.5 | 2.5 | %VOUT | |||
100 µA < IL < 1 A VO + 1 V ≤ VIN ≤ 10 V −40°C ≤ TJ ≤ 125°C |
–5 | 5 | |||||
ΔVOUT/ΔVIN | Output voltage line regulation(2) | VOUT + 0.5 V ≤ VIN ≤ 10 V IL = 25 mA |
0.03 | %/A | |||
VOUT + 0.5 V ≤ VIN ≤ 10 V IL = 25 mA −40°C ≤ TJ ≤ 125°C |
1 | ||||||
ΔVOUT/ΔIL | Output voltage load regulation(3) | 1 mA < IL < 1 A VIN = VOUT + 1 V |
1.8 | V | |||
1 mA < IL < 1 A VIN = VOUT + 1 V −40°C ≤ TJ ≤ 125°C |
5 | ||||||
VIN – VOUT | Dropout voltage(4) | VOUT = 1.8 V IL = 1 A |
950 | mV | |||
VOUT = 1.8 V IL = 1 A −40°C ≤ TJ ≤ 125°C |
1600 | ||||||
VOUT = 2.5 V | IL = 0.1 A | 80 | |||||
IL = 1 A | 800 | ||||||
VOUT = 2.5 V −40°C ≤ TJ ≤ 125°C |
IL = 0.1 A | 145 | |||||
IL = 1 A | 1300 | ||||||
VOUT = 3.3 V | IL = 0.1 A | 65 | |||||
IL = 1 A | 650 | ||||||
VOUT = 3.3 V −40°C ≤ TJ ≤ 125°C |
IL = 0.1 A | 110 | |||||
IL = 1 A | 1000 | ||||||
VOUT = 5 V | IL = 0.1 A | 45 | |||||
IL = 1 A | 450 | ||||||
VOUT = 5 V, −40°C ≤ TJ ≤ 125°C |
IL = 0.1 A | 100 | |||||
IL = 1 A | 800 | ||||||
IQ | Quiescent current | VIN ≤ 10 V, IL = 100 µA to 1 A | 55 | µA | |||
VIN ≤ 10 V, IL = 100 µA to 1 A −40°C ≤ TJ ≤ 125°C |
100 | ||||||
VEN ≤ 0.4 V (LP38692 only) | 0.001 | ||||||
IL(MIN) | Minimum load current | VIN – VOUT ≤ 4 V −40°C ≤ TJ ≤ 125°C |
100 | ||||
IFB | Foldback current limit | VIN – VOUT > 5 V | 450 | mA | |||
VIN – VOUT < 4 V | 1500 | ||||||
PSRR | Ripple rejection | VIN = VOUT + 2 V(DC), with 1V(p-p) / 120 Hz ripple | 55 | dB | |||
TSD | Thermal shutdown activation (junction temp) | 160 | °C | ||||
TSD (HYST) | Thermal shutdown hysteresis (junction temp) | 10 | |||||
en | Output noise | VOUT = 3.3 V, BW = 10 Hz to 10 kHz | 0.7 | µV/√Hz | |||
VOUT (LEAK) | Output leakage current | VOUT = VOUT(NOM) + 1 V at 10 VIN | 0.5 | 12 | µA | ||
VEN | Enable voltage (LP38692 only) | Output = OFF, −40°C ≤ TJ ≤ 125°C | 0.4 | V | |||
Output = ON, VIN = 4 V −40°C ≤ TJ ≤ 125°C |
1.8 | ||||||
Output = ON, VIN = 6 V −40°C ≤ TJ ≤ 125°C |
3 | ||||||
Output = ON, VIN = 10 V −40°C ≤ TJ ≤ 125°C |
4 | ||||||
IEN | Enable pin leakage | VEN = 0 V or 10 V, VIN = 10 V | –1 | 0.001 | 1 | µA |
The LP38690 and LP38692 devices are designed to meet the requirements of portable, battery-powered digital systems providing an accurate output voltage with fast start-up. When disabled via a low logic signal at the enable pin (EN), the power consumption is reduced to virtually zero (LP38692 only). The LP38690 and LP38692 perform well with a single 1-μF input capacitor and a single 1-μF ceramic output capacitor.
The LP38692 has an Enable pin (EN) which allows an external control signal to turn the regulator output On and Off. The Enable On/Off threshold has no hysteresis. The voltage signal must rise and fall cleanly, and promptly, through the ON and OFF voltage thresholds. The EN pin voltage must be higher than the VEN(MIN) threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage must be lower than the VEN(MAX) threshold to ensure that the device is fully disabled. The Enable pin has no internal pull-up or pull-down to establish a default condition and, as a result, this pin must be terminated either actively or passively. If the Enable pin is driven from a source that actively pulls high and low, the drive voltage should not be allowed to go below ground potential or higher than VIN. If the application does not require the Enable function, the pin should be connected directly to the IN pin.
Thermal shutdown disables the output when the junction temperature rises to approximately 160°C which allows the device to cool. When the junction temperature cools to approximately 150°C, the output circuitry enables.
Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a result of overheating.
The TSD circuitry of the LP38692 has been designed to protect against temporary thermal overload conditions. The TSD circuitry was not intended to replace proper heat-sinking. Continuously running the LP38692 device into thermal shutdown degrades device reliability.
Foldback current limiting is built into the LP38690 and LP38692 which reduces the amount of output current the part can deliver as the output voltage is reduced. The amount of load current is dependent on the differential voltage between VIN and VOUT. Typically, when this differential voltage exceeds 5 V, the load current limits at about 450 mA. When the VIN – VOUT differential is reduced below 4 V, load current is limited to about 1500 mA.
CAUTION
When toggling the LP38692 Enable (EN) after the input voltage (VIN) is applied, the foldback current limit circuitry is functional the first time that the EN pin is taken high. The foldback current limit circuitry is non-functional the second, and subsequent, times that the EN pin is taken high. Depending on the input and output capacitance values the input inrush current may be higher than expected which can cause the input voltage to droop.
If the EN pin is connected to the IN pin, the foldback current limit circuitry is functional when VIN is applied if VIN starts from less than 0.4 V.
The EN pin voltage must be higher than the VEN(MIN) threshold to ensure that the device is fully enabled under all operating conditions.
The LP38690 and LP38692 devices do not include any dedicated UVLO circuitry. The LP38690 and LP38692 internal circuitry is not fully functional until VIN is at least 2.7 V. The output voltage is not regulated until VIN ≥ (VOUT + VDO), or 2.7 V, whichever is higher.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
A reverse voltage condition exists when the voltage at the output pin is higher than the voltage at the input pin. Typically this happens when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output voltage becomes reversed. A less common condition is when an alternate voltage source is connected to the output.
There are two possible paths for current to flow from the output pin back to the input during a reverse voltage condition.
If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin must be diode clamped to ground to limit the negative voltage transition. A Schottky diode is recommended for this protective clamp.
For typical CMOS voltage regulator applications, use the parameters listed in Table 1.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Input voltage range | 2.7 to 10 V |
Output voltage | 1.8 V |
Output current | 1 A |
Output capacitor range | 1 µF |
Input/output capacitor ESR range | 5 mΩ to 500 mΩ |
The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the device, to the ultimate heat sink, the ambient environment. Thus, the power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die junction and ambient air.
The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the device, to the ultimate heat sink, the ambient environment. Thus, the power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die junction and ambient air.
The maximum allowable power dissipation for the device in a given package can be calculated using Equation 1:
The actual power being dissipated in the device can be represented by Equation 2:
These two equations establish the relationship between the maximum power dissipation allowed due to thermal consideration, the voltage drop across the device, and the continuous current capability of the device. These two equations should be used to determine the optimum operating conditions for the device in the application.
In applications where lower power dissipation (PD) and/or excellent package thermal resistance (RθJA) is present, the maximum ambient temperature (TA-MAX) may be increased.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature (TA-MAX) may have to be derated. TA-MAX is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by Equation 3:
Alternately, if TA-MAX can not be derated, the PD value must be reduced. This can be accomplished by reducing VIN in the VIN – VOUT term as long as the minimum VIN is met, or by reducing the IOUT term, or by some combination of the two.
In common with most regulators, the LP38690 and LP38692 require external capacitors for regulator stability. The LP38690 and LP38692 are specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance.
An input capacitor is required for stability. It is recommended that a 1-μF capacitor be connected between the LP38690 or LP38692 IN pin and GND pin (this capacitance value may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the IN pin and returned to a clean analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: To ensure stable operation it is essential that good PCB design practices are employed to minimize ground impedance and keep input inductance low. If these conditions cannot be met, or if long leads are used to connect the battery or other power source to the LP38690 or LP38692, then it is recommended that the input capacitor is increased. Also, tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the equivalent series resistance (ESR) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance remains approximately 1 μF over the entire operating temperature range.
The LP38690 and LP38692 are designed specifically to work with very small ceramic output capacitors. A 1-μF ceramic capacitor (temperature types Z5U, Y5V or X7R/X5R) with ESR between 5 mΩ to 500 mΩ, is suitable in the LP38690 or LP38692 application circuit.
For this device the output capacitor should be connected between the OUT pin and GND pin. It is also possible to use tantalum or film capacitors at the device output, but these are not as attractive for reasons of size and cost (see Capacitor Characteristics). The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR value that is within the range 5 mΩ to 500 mΩ for stability.
The LP38690 and LP38692 remain stable and in regulation with no external load. This is an important consideration in some circuits, for example CMOS RAM keep-alive applications.
The LP38690 and LP38692 are designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the range of 0.47 μF to 4.7 μF, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1-μF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability for the LP38690 or LP38692.
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly, depending on the operating conditions and capacitor type.
In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values also shows some decrease over time due to aging. The capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer performance figures in general. As an example, Figure 32 shows a typical graph comparing different capacitor case sizes in a capacitance vs DC bias plot. As shown in Figure 32, increasing the DC Bias condition can result in the capacitance value falling below the minimum value given in the recommended capacitor specifications table (0.7 μF in this case). Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (for example, 0402) may not be suitable in the actual application.
The ceramic capacitor’s value varies with temperature. The capacitor type X7R, which operates over a temperature range of –55°C to 125°C, only varies the capacitance to within ±15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of –55°C to 85°C. Many large value ceramic capacitors, larger than 1 μF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore, X7R and X5R types are recommended over Z5U and Y5V in applications where the ambient temperature changes significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more costly when comparing equivalent capacitance and voltage ratings in the 0.47-μF to 4.7-μF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramic capacitors. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum increases about 2:1 as the temperature goes from 25°C down to -40°C, so some guard band must be allowed.