JAJSA57E September   2003  – August 2016 LP3875-ADJ

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Shutdown (SD)
      2. 7.3.2 Short-Circuit Protection
      3. 7.3.3 Dropout Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Reverse Current Path
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  External Capacitors
        2. 8.2.2.2  CFF (Feed Forward Capacitor)
        3. 8.2.2.3  Selecting a Capacitor
        4. 8.2.2.4  Capacitor Characteristics
          1. 8.2.2.4.1 Ceramic
          2. 8.2.2.4.2 Tantalum
          3. 8.2.2.4.3 Aluminum
        5. 8.2.2.5  Setting The Output Voltage
        6. 8.2.2.6  Turnon Characteristics for Output Voltages Programmed to 2 V or Less
        7. 8.2.2.7  RFI/EMI Susceptibility
        8. 8.2.2.8  Output Noise
        9. 8.2.2.9  Power Dissipation
        10. 8.2.2.10 Estimating Junction Temperature
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops. The input and output capacitors must be directly connected to the IN, OUT, and GND pins of the regulator using traces which do not have other currents flowing in them (Kelvin connect).

The best way to do this is to lay out CIN and COUT near the device with short traces to the IN, OUT, and GND pins. Connect the GND pin to the external circuit ground so that the regulator and its capacitors have a single-point ground.

Note that stability problems have been seen in applications where vias to an internal ground plane were used at the ground points of the device and the input and output capacitors. This was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane. Using a single-point ground technique for the regulator and its capacitors solved the problem.

Because high current flows through the traces going into VIN and coming from VOUT, Kelvin connect the capacitor leads to these pins so there is no voltage drop in series with the input and output capacitors.

10.2 Layout Examples

LP3875-ADJ KTT_layout.gif Figure 14. Layout Example for DDPAK/TO-263 Package
LP3875-ADJ NDC_layout.gif Figure 15. Layout Example for SOT-223 Package