JAJSAB5F December 2006 – November 2016 LP38853
PRODUCTION DATA.
A reverse voltage condition exists when the voltage at the output pin is higher than the voltage at the IN pin. Typically this happens when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output voltage becomes reversed.
The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass element is not driven, there is no reverse current flow through the pass element during a reverse voltage event. The gate of the pass element is not driven when VBIAS is below the UVLO threshold, or when the EN pin is held low.
When VBIAS is above the UVLO threshold, and the EN pin is above the VEN(ON) threshold, the control circuitry is active and attempts to regulate the output voltage. Because the input voltage is less than the output voltage the control circuit drives the gate of the pass element to the full VBIAS potential when the output voltage begins to fall. In this condition, reverse current flows from the OUT pin to the IN pin , limited only by the RDS(ON) of the pass element and the output-to-input voltage differential. Discharging an output capacitor up 1000 µF in this manner does not damage the device as the current rapidly decays. However, continuous reverse current must be avoided.