JAJSAB5F December   2006  – November 2016 LP38853

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO)
      2. 7.3.2 Supply Sequencing
      3. 7.3.3 Reverse Voltage
      4. 7.3.4 Soft-Start
      5. 7.3.5 Setting The Output Voltage
      6. 7.3.6 Enable (EN) Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Input Voltage
      2. 7.4.2 Bias Voltage
      3. 7.4.3 Enable Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
          1. 8.2.2.1.1 Input Capacitor
          2. 8.2.2.1.2 Output Capacitor
          3. 8.2.2.1.3 Bias Capacitor
          4. 8.2.2.1.4 Set The Output Voltage
          5. 8.2.2.1.5 Feed Forward Capacitor, CFF
        2. 8.2.2.2 Power Dissipation and Heat Sinking
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報
  13. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.5 Setting The Output Voltage

The output voltage is set using the external resistive divider R1 and R2 (see Figure 23). The output voltage is given by Equation 2:

Equation 2. LP38853 20131051.gif

The resistors used for R1 and R2 must be high quality, tight tolerance, and with matching temperature coefficients. It is important to remember that, although the value of VADJ is specified, the use of low-quality resistors for R1 and R2 can easily produce a VOUT value that is unacceptable.

It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 kΩ. This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the FZ pole set by R1 and CFF.

Equation 3. ((R1 × R2) / (R1 + R2) ) ≤ 10 kΩ

Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10% capacitor values for CFF, for a range of VOUT values. Other values of R1, R2, and CFF are available that give similar results.

Table 1. Suggested Resistor Values

VOUTR1R2CFFFZ
0.8 V 1.07 kΩ 1.78 kΩ 12 nF 12.4 kHz
0.9 V 1.50 kΩ 1.87 kΩ 8.2 nF 12.9 kHz
1 V 1.00 kΩ 1.00 kΩ 12 nF 13.3 kHz
1.1 V 1.65 kΩ 1.37 kΩ 8.2 nF 11.8 kHz
1.2 V 1.40 kΩ 1.00 kΩ 10 nF 11.4 kHz
1.3 V 1.15 kΩ 715 Ω 12 nF 11.5 kHz
1.4 V 1.07 kΩ 590 Ω 12 nF 12.4 kHz
1.5 V 2.00 kΩ 1.00 kΩ 6.8 nF 11.7 kHz
1.6 V 1.65 kΩ 750 Ω 8.2 nF 11.8 kHz
1.7 V 2.55 kΩ 1.07 kΩ 5.6 nF 11.1 kHz
1.8 V 2.94 kΩ 1.13 kΩ 4.7 nF 11.5 kHz

Refer to the TI Application Note AN-1378 Method for Calculating Output Voltage Tolerances in Adjustable Regulators (SNVA112) for additional information on how resistor tolerances affect the calculated VOUT value.