JAJSAB5F December   2006  – November 2016 LP38853

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO)
      2. 7.3.2 Supply Sequencing
      3. 7.3.3 Reverse Voltage
      4. 7.3.4 Soft-Start
      5. 7.3.5 Setting The Output Voltage
      6. 7.3.6 Enable (EN) Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Input Voltage
      2. 7.4.2 Bias Voltage
      3. 7.4.3 Enable Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
          1. 8.2.2.1.1 Input Capacitor
          2. 8.2.2.1.2 Output Capacitor
          3. 8.2.2.1.3 Bias Capacitor
          4. 8.2.2.1.4 Set The Output Voltage
          5. 8.2.2.1.5 Feed Forward Capacitor, CFF
        2. 8.2.2.2 Power Dissipation and Heat Sinking
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報
  13. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.1.5 Feed Forward Capacitor, CFF

When using a ceramic capacitor for COUT, the typical ESR value may be too small to provide any meaningful positive phase compensation, FZ, to offset the internal negative phase shifts in the gain loop (see Figure 23 and Equation 4).

Equation 4. FZ = (1 / (2 × π × COUT × ESR))

A capacitor placed across the gain resistor R1 provides additional phase margin to improve load transient response of the device. This capacitor, CFF, in parallel with R1, forms a zero in the loop response given by Equation 5:

Equation 5. FZ = (1 / (2 × π × CFF × R1))

For optimum load transient response select CFF so the zero frequency, FZ, falls between 10 kHz and 15 kHz as shown in Equation 6:

Equation 6. (CFF = (1 / (2 × π × R1 × FZ)

The phase lead provided by CFF diminishes as the DC gain approaches unity, or VOUT approaches VADJ. This is because CFF also forms a pole with a frequency shown in Equation 7:

Equation 7. FP = (1 / (2 × π × CFF × (R1 || R2) ))

NOTE

It is important to note that at higher output voltages, where R1 is much larger than R2, the pole and zero are far apart in frequency. At lower output voltages the frequency of the pole and the zero move closer together. The phase lead provided from CFF diminishes quickly as the output voltage is reduced, and has no effect when VOUT = VADJ. For this reason, relying on this compensation technique alone is adequate only for higher output voltages. For the LP38853, the practical minimum VOUT is 0.8 V when a ceramic capacitor is used for COUT.

LP38853 20131021.pngFigure 24. FZERO and FPOLE vs Gain