JAJSAB5F December   2006  – November 2016 LP38853

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO)
      2. 7.3.2 Supply Sequencing
      3. 7.3.3 Reverse Voltage
      4. 7.3.4 Soft-Start
      5. 7.3.5 Setting The Output Voltage
      6. 7.3.6 Enable (EN) Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Input Voltage
      2. 7.4.2 Bias Voltage
      3. 7.4.3 Enable Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
          1. 8.2.2.1.1 Input Capacitor
          2. 8.2.2.1.2 Output Capacitor
          3. 8.2.2.1.3 Bias Capacitor
          4. 8.2.2.1.4 Set The Output Voltage
          5. 8.2.2.1.5 Feed Forward Capacitor, CFF
        2. 8.2.2.2 Power Dissipation and Heat Sinking
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報
  13. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.2 Power Dissipation and Heat Sinking

Additional copper area for heat sinking may be required, depending on the maximum device dissipation (PD) and the maximum anticipated ambient temperature (TA) for the device. Under all possible conditions, the junction temperature must be within the range specified under operating conditions.

The total power dissipation of the device is the sum of three different points of dissipation in the device.

The first part is the power that is dissipated in the NMOS pass element and can be determined with Equation 8:

Equation 8. PD(PASS) = (VIN – VOUT) × IOUT

The second part is the power that is dissipated in the bias and control circuitry and can be determined with Equation 9:

Equation 9. PD(BIAS) = VBIAS × IGND(BIAS)

where

  • IGND(BIAS) is the portion of the operating ground current of the device that is related to VBIAS.

The third part is the power that is dissipated in portions of the output stage circuitry and can be determined with Equation 10:

Equation 10. PD(IN) = VIN × IGND(IN)

where

  • IGND(IN) is the portion of the operating ground current of the device that is related to VIN.

The total power dissipation is shown by Equation 11:

Equation 11. PD = PD(PASS) + PD(BIAS) + PD(IN)

The maximum allowable junction temperature rise (ΔTJ) depends on the maximum anticipated ambient temperature (TA(MAX)) for the application, and the maximum allowable operating junction temperature (TJ(MAX))(see Equation 12):

Equation 12. ΔTJ = TJ(MAX) – TA(MAX)

The maximum allowable value for junction-to-ambient thermal resistance, RθJA, can be calculated using Equation 13:

Equation 13. LP38853 20131058.gif