JAJSED9U June   2007  – January 2018 LP3907

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
  4. 4 改訂履歴
  5. 5 デバイス比較表
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions (Bucks)
    4. 7.4  Thermal Information
    5. 7.5  General Electrical Characteristics
    6. 7.6  Low Dropout Regulators, LDO1 And LDO2
    7. 7.7  Buck Converters SW1, SW2
    8. 7.8  I/O Electrical Characteristics
    9. 7.9  Power-On Reset (POR) Threshold/Function
    10. 7.10 I2C Interface Timing Requirements
    11. 7.11 Typical Characteristics — LDO
    12. 7.12 Typical Characteristics — Bucks
    13. 7.13 Typical Characteristics — Buck1
    14. 7.14 Typical Characteristics — Buck2
    15. 7.15 Typical Characteristics — Bucks
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DC-DC Converters
        1. 8.3.1.1 Linear Low Dropout Regulators (LDOs)
        2. 8.3.1.2 No-Load Stability
        3. 8.3.1.3 LDO and LDO2 Control Registers
      2. 8.3.2 SW1, SW2: Synchronous Step-Down Magnetic DC-DC Converters
        1. 8.3.2.1  Functional Description
        2. 8.3.2.2  Circuit Operation Description
        3. 8.3.2.3  PWM Operation
        4. 8.3.2.4  Internal Synchronous Rectification
        5. 8.3.2.5  Current Limiting
        6. 8.3.2.6  PFM Operation
        7. 8.3.2.7  SW1, SW2 Operation
        8. 8.3.2.8  SW1, SW2 Control Registers
        9. 8.3.2.9  Soft Start
        10. 8.3.2.10 Low Dropout Operation
        11. 8.3.2.11 Flexible Power Sequencing of Multiple Power Supplies
        12. 8.3.2.12 Power-Up Sequencing Using the EN_T Function
      3. 8.3.3 Flexible Power-On Reset (Power Good with Delay)
      4. 8.3.4 Undervoltage Lockout
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Serial Interface
        1. 8.5.1.1 I2C Signals
        2. 8.5.1.2 I2C Data Validity
        3. 8.5.1.3 I2C Start and Stop Conditions
        4. 8.5.1.4 Transferring Data
      2. 8.5.2 Factory Programmable Options
    6. 8.6 Register Maps
      1. 8.6.1 LP3907 Control Registers
        1. 8.6.1.1  Interrupt Status Register (ISRA) 0x02
        2. 8.6.1.2  Control 1 Register (SCR1) 0x07
        3. 8.6.1.3  EN_DLY Preset Delay Sequence After EN_T Assertion
        4. 8.6.1.4  Buck and LDO Output Voltage Enable Register (BKLDOEN) – 0x10
        5. 8.6.1.5  Buck and LDO Status Register (BKLDOSR) – 0x11
        6. 8.6.1.6  Buck Voltage Change Control Register 1 (VCCR) – 0x20
        7. 8.6.1.7  Buck1 Target Voltage 1 Register (B1TV1) – 0x23
        8. 8.6.1.8  Buck1 Target Voltage 2 Register (B1TV2) – 0x24
        9. 8.6.1.9  Buck1 Ramp Control Register (B1RC) - 0x25
        10. 8.6.1.10 Buck2 Target Voltage 1 Register (B2TV1) – 0x29
        11. 8.6.1.11 Buck2 Target Voltage 2 Register (B2TV2) – 0x2A
        12. 8.6.1.12 Buck2 Ramp Control Register (B2RC) - 0x2B
        13. 8.6.1.13 Buck Function Register (BFCR) – 0x38
        14. 8.6.1.14 LDO1 Control Register (LDO1VCR) – 0x39
        15. 8.6.1.15 LDO2 Control Register (LDO2VCR) – 0x3A
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Component Selection
          1. 9.2.2.2.1 Inductors for SW1 And SW2
            1. 9.2.2.2.1.1 Method 1:
            2. 9.2.2.2.1.2 Method 2:
          2. 9.2.2.2.2 External Capacitors
        3. 9.2.2.3 LDO Capacitor Selection
          1. 9.2.2.3.1 Input Capacitor
          2. 9.2.2.3.2 Output Capacitor
          3. 9.2.2.3.3 Capacitor Characteristics
          4. 9.2.2.3.4 Input Capacitor Selection for SW1 And SW2
          5. 9.2.2.3.5 Output Capacitor Selection for SW1, SW2
          6. 9.2.2.3.6 I2C Pullup Resistor
        4. 9.2.2.4 Operation Without I2C Interface
          1. 9.2.2.4.1 High VIN High-Load Operation
          2. 9.2.2.4.2 Junction Temperature
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Analog Power Signal Routing
  11. 11Layout
    1. 11.1 DSBGA Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations of WQFN Package
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 商標
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 コミュニティ・リソース
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.3.5 Output Capacitor Selection for SW1, SW2

A 10-μF, 6.3-V ceramic capacitor must be used on the output of the SW1 and SW2 magnetic DC-DC converters. The output capacitor must be mounted as close to the output of the device as possible. A large value may be used for improved input voltage filtering. The recommended capacitor types are X7R or X5R. Y5V type capacitors should not be used. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer, and DC bias curves should be requested from them and analyzed as part of the capacitor selection process.

The output filter capacitor of the magnetic DC-DC converter smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESD to perform these functions.

The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its ESR and can be calculated as follows:

Equation 9. LP3907 30017832.gif

Voltage peak-to-peak ripple due to ESR can be expressed as follows:

Equation 10. VPP–ESR = 2 × IRIPPLE × RESR

Because the VPP-C and VPP-ESR are out of phase, the rms value can be used to get an approximate value of the peak-to-peak ripple:

Equation 11. LP3907 30017833.gif

Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the output capacitor (RESR). The RESR is frequency dependent as well as temperature dependent. Calculate the RESR with the applicable switching frequency and ambient temperature.

Table 9. Suggested Capacitor Values

CAPACITOR MIN VALUE (µF) DESCRIPTION RECOMMENDED TYPE
CLDO1 0.47 LDO1 output capacitor Ceramic, 6.3 V, X5R
CLDO2 0.47 LDO2 output capacitor Ceramic, 6.3 V, X5R
CSW1 10 SW1 output capacitor Ceramic, 6.3 V, X5R
CSW2 10 SW2 output capacitor Ceramic, 6.3 V, X5R