SNVS468 Data sheet

SNVS468L September 2006 – November 2015 LP3972

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RSB|40
- MPQF185C

サーマルパッド・メカニカル・データ

発注情報

6 Pin Configuration and Functions

RSB Package

40-Pin WQFN

Top View

RSB Package

40-Pin WQFN

Bottom View

Pin Functions

PIN		I/O	TYPE⁽¹⁾	DESCRIPTION
NUMBER	NAME⁽²⁾	I/O	TYPE⁽¹⁾	DESCRIPTION
1	PWR_ON	I	D	This is an active HI push button input which can be used to signal PWR_ON and PWR_OFF events to the CPU by controlling the EXT_WAKEUP [pin4] and select contents of register 8H'88.
2	nTEST_JIG	I	D	This is an active LOW input signal used for detecting an external HW event. The response is seen in the EXT_WAKEUP [pin4] and select contents of register 8H'88.
3	SPARE	I	D	This is an input signal used for detecting a external HW event. The response is seen in the EXT_WAKEUP [pin4] and select contents of register 8H'88. The polarity on this pin is assignable.
4	EXT_WAKEUP	O	D	This pin generates a single 10-ms pulse output to CPU in response to input from pins 1, 2, and 3. Flags CPU to interrogate register 8H'88.
5	FB1	I	A	Buck1 input feedback pin.
6	V_IN	I	PWR	Battery input (internal circuitry and LDO1-3 power input)
7	VOUT LDO1	O	PWR	LDO1 output
8	VOUT LDO2	O	PWR	LDO2 output
9	nRSTI	I	D	Active low reset pin. Signal used to reset the device (by default is pulled high internally). Typically a push button reset.
10	GND1	G	G	Ground
11	VREF	O	A	Bypass capacitor for the high internal impedance reference.
12	VOUT LDO3	O	PWR	LDO3 output
13	VOUT LDO4	O	PWR	LDO4 output
14	VIN LDO4	I	PWR	Power input to LDO4 — this can be connected to either from a 1.8-V supply to main battery supply.
15	VIN BUBATT	I	PWR	Backup battery input supply.
16	VOUT LDO_RTC	O	PWR	LDO_RTC output supply to the RTC of the application processor.
17	nBATT_FLT	O	D	Main battery fault output, indicates the main battery is low (discharged) or the DC source has been removed from the system. This gives the processor an indicator that the power will shut down. During this time the processor will operate from the backup coin cell.
18	PGND2	G	G	Buck2 NMOS power ground
19	SW2	O	PWR	Buck2 switcher output
20	VIN BUCK2	I	PWR	Battery input power to Buck2
21	SDA	I/O	D	I²C Data (Bidirectional)
22	SCL	I	D	I²C Clock
23	FB2	I	A	Buck2 input feedback pin
24	nRSTO	O	D	Reset output from the PMIC to the processor
25	VOUT LDO5	O	PWR	LDO5 output
26	VIN LDO5	I	PWR	Power input to LDO5, this can be connected to V_IN or to a separate 1.8-V supply.
27	VDDA	I	PWR	Analog Power for VREF, BIAS
28	FB3	I	A	Buck3 Feedback
29	GPIO1 / nCHG_EN	I/O	D	General purpose I/O / Ext. backup battery charger enable pin. This pin enables the main battery or DC source power to charge the backup battery. This pin toggled via the application processor. By grounding this pin the DC source continuously charges the backup battery.
30	GPIO2	I/O	D	General purpose I/O
31	VIN BUCK3	I	PWR	Battery input power to Buck3
32	SW3	O	PWR	Buck3 switcher output
33	PGND3	G	G	Buck3 NMOS Power ground
34	BGND1,2,3	G	G	Bucks 1, 2 and 3 analog ground
35	SYNC	I	D	Frequency synchronization: Connection to an external clock signal PLL to synchronize the PMIC internal oscillator.
36	SYS_EN	I	D	Input digital enable pin for the high voltage power domain supplies. Output from the Monahans processor.
37	PWR_EN	I	D	Digital enable pin for the low-voltage domain supplies. Output signal from the Monahans processor
38	PGND1	G	G	Buck1 NMOS power ground
39	SW1	O	PWR	Buck1 switcher output
40	VIN BUCK1	I	PWR	Battery input power to Buck1

(1) A: Analog Pin D: Digital Pin G: Ground Pin P: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin

(2) In this document, active-low logic items are prefixed with a lowercase "n".