7.3.5.1 Overview

The LP55231 includes a pre-regulated switched-capacitor charge pump with a programmable voltage multiplication of 1 and 1.5×. In 1.5× mode, by combining the principles of a switched-capacitor charge pump and a linear regulator, a regulated 4.5 V output is generated from the Li-Ion input voltage range. A two-phase non-overlapping clock generated internally controls the operation of the charge pump. During the charge phase, both flying capacitors (C1 and C2) are charged from input voltage. In the pump phase that follows, the flying capacitors are discharged to output. A traditional switched-capacitor charge pump operating in this manner use switches with very low on-resistance, ideally 0 Ω, to generate an output voltage that is 1.5× the input voltage. The LP55231 regulates the output voltage by controlling the resistance of the input-connected pass-transistor switches in the charge pump.

7.3.5.2 Output Resistance

At lower input voltages, the charge pump output voltage may degrade due to effective output resistance (R_OUT) of the charge pump. The expected voltage drop can be calculated by using a simple model for the charge pump shown in Figure 14.

Figure 14. Charge Pump Output Resistance Model

The model shows a linear pre-regulation block (REG), a voltage multiplier (1.5×), and an output resistance (R_OUT). Output resistance models the output voltage drop that is inherent to switched capacitor converters. The output resistance is 3.5Ω (typ.), and it is a function of switching frequency, input voltage, flying capacitors’ capacitance value, internal resistances of the switches and ESR of the flying capacitors. When the output voltage is in regulation, the regulator in the model controls the voltage V’ to keep the output voltage equal to 4.5 V (typical).

With increased output current, the voltage drop across R_OUT increases. To prevent drop in output voltage, the voltage drop across the regulator is reduced, V’ increases, and V_OUT remains at 4.5 V. When the output current increases to the point that there is zero voltage drop across the regulator, V’ equals the input voltage, and the output voltage is on the edge of regulation. Additional output current causes the output voltage to fall out of regulation, so that the operation is similar to a basic open-loop 1.5× charge pump. In this mode, output current results in output voltage drop proportional to the output resistance of the charge pump. The out-of-regulation output voltage can be approximated by: V_OUT = 1.5 × V_IN – I_OUT × R_OUT.

7.3.5.3 Controlling The Charge Pump

The charge pump is controlled with two CP_MODE bits in MISC register (address 36H). When both of the bits are low, the charge pump is disabled, and output voltage is pulled down with an internal 300-kΩ (typical) resistor. The charge pump can be forced to bypass mode, so the battery voltage is connected directly to the current sources; in 1.5× mode output voltage is boosted to 4.5 V. In automatic mode, charge-pump operation mode is determined by saturation of constant current drivers, as described in LED Forward Voltage Monitoring.

7.3.5.4 LED Forward Voltage Monitoring

When the charge-pump automatic mode selection is enabled, voltages over LED drivers D1 to D6 are monitored.

If the D1 to D6 drivers do not have enough headroom, charge-pump gain is set to 1.5×. Driver saturation monitor does not have a fixed voltage limit, since saturation voltage is a function of temperature and current. Charge pump gain is set to 1×, when battery voltage is high enough to supply all LEDs.

In automatic gain change mode, the charge pump is switched to bypass mode (1×), when LEDs are inactive for over 50 ms.

7.3.5.5 Gain Change Hysteresis

Charge pump gain control utilizes digital filtering to prevent supply voltage disturbances (for example, the transient voltage on the power supply during the GSM burst) from triggering unnecessary gain changes. Hysteresis is provided to prevent periodic gain changes (which could occur due to LED driver) and charge-pump voltage drop in 1× mode. The hysteresis of the gain change is user-configurable; default setting is factory-programmable. Flexible configuration ensures that hysteresis can be minimized or set to desired level in each application.

LED forward voltage monitoring and gain control block diagram is shown in Figure 15.

Figure 15. Forward Voltage Monitoring and Gain Control Block

7.3.6.1 Overview

LP55231 LED drivers are constant current sources. Output current can be programmed by control registers up to 25.5 mA. The overall maximum current is set by 8-bit output current control registers with 100-μA step size. Each of the 9 LED drivers has a separate output current control register.

The LED luminance pattern (dimming) is controlled with PWM (pulse width modulation) technique, which has internal resolution of 12 bits (8-bit control can be seen by user). PWM frequency is 312 Hz. See Figure 16.

Figure 16. LED Pattern and Current Control Principle

LED dimming is controlled according to a logarithmic or linear scale, see Figure 17. A logarithmic or linear scheme can be set for both the program execution engine control and direct PWM control. Note: if the temperature compensation is active, the maximum PWM duty cycle is limited to 50% at 25°C. This is required to allow enough headroom for temperature compensation over the whole temperature range −30°C to +90°C.

Figure 17. Logarithmic vs Linear Dimming

7.3.6.2 Powering LEDs

The LP55231 is very suitable for white LED and general purpose applications, and it is particularly well suited to use with RGB LEDs. The LP55231 architecture is optimized for use with three RGB LEDs. Typically, the red LEDs have forward voltages below 2 volts, thus red LEDs can be powered directly from V_DD. In the LP55231 D7, D8, and D9 drivers are powered from the battery voltage (V_DD), not from the charge-pump output. D1 to D6 drivers are internally connected to the charge-pump output, and these outputs can be used for driving green and blue (V_F = 2.7 V to 3.7 V typical) or white LEDs. Of course, D7, D8, and D9 outputs can be used for green, blue or white LEDs if the V_DD voltage is high enough.

An RGB LED configuration example is given in the Typical Applications.

7.3.6.3 Controlling The High-Side LED Drivers

1. Direct PWM Control: All LP55231 LED drivers, D1 to D9, can be controlled independently through the two-wire serial I²C-compatible interface. For each high-side driver there is a PWM control register. Direct PWM control is active by default.
2. Controlling by Program Execution Engines: Engine control is used when the user wants to create programmed sequences. The program execution engine has a higher priority than direct control registers. Therefore, if the user has set the PWM register to a certain value, it is automatically overridden when the program execution engine controls the driver. LED control and program execution engine operation is described in Control Register Details.
3. Master Fader Control: In addition to LED-by-LED PWM register control, the LP55231 is equipped with master fader control, which allows the user to fade in or fade out multiple LEDs by writing to only one register. This is a useful function to minimize serial bus traffic between the MCU and the LP55231. The LP55231 has three master fader registers, so it is possible to form three master fader groups.

7.5.1.1 Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when clock signal is LOW.

Figure 20. Data Validity Diagram

7.5.1.2 Start And Stop Conditions

START and STOP conditions classify the beginning and the end of the data transfer session. A START condition is defined as the SDA signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The bus master always generates START and STOP conditions. The bus is considered to be busy after a START condition and free after a STOP condition. During data transmission, the bus master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise.

7.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP55231 pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP55231 generates an acknowledge after each byte has been received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must indicate to the transmitter an end of data by not acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

After the START condition, the bus master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). The LP55231 address is defined with ASEL0 and ASEL1 pins, and it is 32h when ASEL1 and ASEL0 are connected to GND. For the eighth bit, a 0 indicates a WRITE, and a 1 indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register.

Table 1. LP55231 Chip Address Configuration

7.5.2.1 Control Register Write Cycle

• Master device generates start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master sends data byte to be written to the addressed register.
• Slave sends acknowledge signal.
• If master sends further data bytes, the slave’s control register address is incremented by one after acknowledge signal. In order to reduce program load time, the LP55231 supports address auto incrementation. Register address is incremented after each 8 data bits. For example, the whole program memory page can be written in one serial bus write sequence. Note: serial bus address auto increment is not supported for register addresses from 16 to 1E.
• Write cycle ends when the master creates stop condition.

7.5.2.2 Control Register Read Cycle

• Master device generates a start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master device generates repeated start condition.
• Master sends the slave address (7 bits) and the data direction bit (r/w = 1).
• Slave sends acknowledge signal if the slave address is correct.
• Slave sends data byte from addressed register.
• If the master device sends an acknowledge signal, the control register address is incremented by one. Slave device sends data byte from addressed register.
• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition

7.5.2.3 Auto-Increment Feature

The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-bit word is sent to the LP55231, the internal address index counter is incremented by one, and the next register is written. Table 2 shows writing sequence to two consecutive registers. Auto-increment feature is enabled by writing EN_AUTO_INCR bit high in the MISC register (addr 36h). Note: serial bus address auto increment is not supported for register addresses from 16 to 1E.

Table 3. Control Register Map

Table 4. LP55231 LED Driver Instructions

Table 5. LP55231 LED Mapping Instructions

Table 6. LP55231 Branch Instructions

Table 7. LP55231 Data Transfer and Arithmetic Instructions

7.6.4.1 Ramp

This is the instruction useful for smoothly changing from one PWM value into another PWM value on the D1 to D9 outputs; in other words, generating ramps (with a negative or positive slope). The LP55231 allows programming very fast and very slow ramps.

Ramp instruction generates a PWM ramp, using the effective PWM value as a starting value. At each ramp step the output is incremented/decremented by one unit, unless the number of increments is 0. Time span for one ramp step is defined with prescale bit [14] and step time bits [13:9]. Prescale = 0 sets 0.49 ms cycle time and prescale = 1 sets 15.6 ms cycle time; so the minimum time span for one step is 0.49 ms (prescale × step time span = 0.49 ms × 1) and the maximum time span is 15.6 ms × 31 = 484 ms/step.

Number of increments value defines how many steps are taken during one ramp instruction; increment maximum value is 255d, which corresponds increment from zero value to the maximum value. If PWM reaches minimum/maximum value (0/255) during the ramp instruction, ramp instruction is executed to the end regardless of saturation. This enables ramp instruction to be used as a combined ramp and wait instruction. Note: Ramp instruction is wait instruction when the increment bits [7:0] are set to zero.

Programming ramps with variables is very similar to programming ramps with numerical operands. The only difference is that step time and number of increments are captured from variable registers, when the instruction execution is started. If the variables are updated after starting the instruction execution, it has no effect on instruction execution. Again, at each ramp step the output is incremented/decremented by one unless increment is 0. Time span for one step is defined with prescale and step time bits. Step time is defined with variable A, B, C or D. Variables A, B and C are set with ld-instruction. Variable D is a global variable and can be set by writing the VARIABLE register (address 3C). LED TEST ADC register (address 42) can be used as a source for the variable D, as well. Note: Variable A is the only local variable which can be read throughout the serial bus. Of course, the variable stored in 3CH can be read (and written), too.

Setting register 06H, 07H, or 08H bit LOG_EN high/low sets logarithmic (1) or linear ramp (0). By using the logarithmic ramp setting the visual effect appears like a linear ramp, because the human eye behaves in a logarithmic way.

7.6.4.2 Ramp Instruction Application Example

Suppose that the LED dimming is controlled according to the linear scale and effective PWM value at the moment t = 0 is 140d (approximately 55%), as shown in the figure below, and we want to reach a PWM value of 148d (approximately 58%) at the moment t = 1.5 s. The parameters for the RAMP instruction are:

• Prescale = 1 → 15.625 ms cycle time
• Step time = 12 → step time span is 12 × 15.625 ms = 187.5 ms
• Sign = 0 → increase PWM output
• # of increments = 8 → take 8 steps

Figure 26. Example Of Ramp Instruction

7.6.4.3 Set_PWM

This instruction is used for setting the PWM value on the outputs D1 to D9 without any ramps. Set PWM output value from 0 to 255 with PWM value bits [7:0]. Instruction execution takes sixteen 32-kHz clock cycles (=488 µs).

7.6.4.4 Wait

When a wait instruction is executed, the engine is set in wait status, and the PWM values on the outputs are frozen.

7.6.5.1 MUX_LD_START; MUX_LD_END

Mux_ld_start and mux_ld_end define the mapping table location in the memory.

7.6.5.2 MUX_MAP_START

Mux_map_start defines the mapping table start address in the memory, and the first row of the table is activated (mapped) at the same time.

7.6.5.3 MUX_SEL

With mux_sel instruction one, and only one, LED driver can be connected to a program execution engine. Connecting multiple LEDs to one engine is done with the mapping table. After the mapping has been released from an LED, PWM register value still controls the LED brightness.

7.6.5.4 MUX_CLR

Mux_clr clears engine-to-driver mapping. After the mapping has been released from an LED, the PWM register value still controls the LED brightness.

7.6.5.5 MUX_MAP_NEXT

This instruction sets the next row active in the mapping table each time it is called. For example, if the 2nd row is active at this moment, after mux_map_next instruction call the 3rd row is active. If the mapping table end address is reached, activation rolls to the mapping table start address next time when the mux_map_next instruction is called. The engine does not push a new PWM value to the LED driver output before set_pwm or ramp instruction is executed. If the mapping has been released from an LED, the value in the PWM register still controls the LED brightness.

7.6.5.6 MUX_LD_NEXT

Similar than the mux_map_next instruction, but only the index pointer is set to point to the next row; that is, no mapping is set, and the engine-to-LED-driver connection is not e updated.

7.6.5.7 MUX_MAP_PREV

This instruction sets the previous row active in the mapping table each time it is called. For example, if the 3rd row is active at this moment, after mux_map_prev instruction call the 2nd row is active. If the mapping table start address is reached, activation rolls to the mapping table end address next time the mux_map_prev instruction is called. Engine does not push a new PWM value to the LED driver output before set_pwm or ramp instruction is executed. If the mapping has been released from an LED, the value in the PWM register still controls the LED brightness.

7.6.5.8 MUX_LD_PREV

Similar than the mux_map_prev instruction, but only the index pointer is set to point to the previous row; that is, no mapping is set, and the engine-to-LED-driver connection is not updated.

7.6.5.9 MUX_MAP_ADDR

Mux_map_addr sets the index pointer to point the mapping table row defined by bits [6:0] and sets the row active. The engine does not push a new PWM value to the LED driver output before set_pwm or ramp instruction is executed. If the mapping has been released from an LED, the value in the PWM register still controls the LED brightness.

7.6.5.10 MUX_LD_ADDR

Mux_ld_addr sets the index pointer to point the mapping table row defined by bits [6:0], but the row is not set active.

7.6.6.1 BRANCH

Branch instruction is mainly indented for repeating a portion of the program code several times. Branch instruction loads step number value to program counter. Loop count parameter defines how many times the instructions inside the loop are repeated. The LP55231 supports nested looping, that is, loop inside loop. The number of nested loops is not limited. Instruction takes sixteen 32-kHz clock cycles.

7.6.6.2 INT

Send interrupt to processor by pulling the INT pin down and setting corresponding status bit high. Interrupt can be cleared by reading interrupt bits in STATUS/INTERRUPT register at address 3A.

7.6.6.3 RST

Rst instruction resets Program Counter register (address 37H, 38H, or 39H) and continues executing the program from the program start address defined in 4C-4E. Instruction takes sixteen 32-kHz clock cycles. Note that default value for all program memory registers is 0000H, which is the rst instruction.

7.6.6.4 END

End program execution. Instruction takes sixteen 32-kHz clock cycles.

7.6.6.5 TRIGGER

Wait or send triggers can be used to, for example, synchronize operation between the program execution engines. Send trigger instruction takes sixteen 32-kHz clock cycles and wait for trigger takes at least sixteen 32-kHz clock cycles. The receiving engine stores the triggers which have been sent. Received triggers are cleared by wait for trigger instruction. Wait for trigger instruction is executed until all the defined triggers have been received. (Note: several triggers can be defined in the same instruction.)

External trigger input signal must stay low for at least two 32-kHz clock cycles to be executed. Trigger output signal is three 32-kHz clock cycles long. External trigger signal is active low, for example, when trigger is sent/received the pin is pulled to GND. Send external trigger is masked; that is, the device which has sent the trigger does not recognize it. If send and wait external trigger are used on the same instruction, the send external trigger is executed first, then the wait external trigger.

The LP55231 instruction set includes the following conditional jump instructions: jne (jump if not equal); jge (jump if greater or equal); jl (jump if less); je (jump if equal). If the condition is true, a certain number of instructions are skipped (that is, the program jumps forward to a location relative to the present location). If condition is false, the next instruction is executed.

7.6.7.1 LD

This instruction is used to assign a value into a variable; the previous value in that variable is overwritten. Each of the engines have two local variables, called A and B. The variable C is a global variable.

7.6.7.2 ADD

Operator either adds 8-bit value to the current value of the target variable, or adds the value of the variable 1 (A, B, C or D) to the value of the variable 2 (A, B, C or D) and stores the result in the register of variable A, B or C. Variables overflow from 255 to 0.

7.6.7.3 SUB

SUB Operator either subtracts 8-bit value from the current value of the target variable, or subtracts the value of the variable 2 (A, B, C or D) from the value of the variable 1 (A, B, C or D) and stores the result in the register of target variable (A, B or C). Variables overflow from 0 to 255.