The below guidelines for layout design can help to get a better on-board performance.

• The decoupling capacitors C_VCC and C_VLED for power supply must be close to the chip to have minimized the impact of high-frequency noise and ripple from power. C_VCAP for internal LDO must be put as close to chip as possible. GND plane connections to C_VLED and GND pins must be on TOP layer copper with multiple vias connecting to system ground plane. C_VIO for internal enable block also must be put as close to chip as possible.
• The exposed thermal pad must be well soldered to the board, which can have better mechanical reliability. This action can optimize heat transfer so that increasing thermal performance. AGND pin must be connected to thermal pad and system ground.
• The major heat flow path from the package to the ambient is through copper on the PCB. Several methods can help thermal performance. Below exposed thermal pad of IC, putting much vias through the PCB to other ground layer can dissipate more heat. Maximizing the copper coverage on the PCB can increase the thermal conductivity of the board.
• Low inductive and resistive path of switch load loop can help to provide a high slew rate. Therefore, path of VLED – SWx must be short and wide and avoid parallel wiring and narrow trace. Transient current in SWx pins is much larger than CSy pins, so that trace for SWx must be wider than CSy.