JAJSOY5A may   2023  – august 2023 LP5861T

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7.     15
    8. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Dimming (Current Gain Control)
      2. 8.3.2 PWM Dimming
      3. 8.3.3 ON and OFF Control
      4. 8.3.4 Data Refresh Mode
      5. 8.3.5 Full Addressable SRAM
      6. 8.3.6 Protections and Diagnostics
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 CONFIG Registers
      2. 8.6.2 GROUP Registers
      3. 8.6.3 DOTGROUP Registers
      4. 8.6.4 DOTONOFF Registers
      5. 8.6.5 FAULT Registers
      6. 8.6.6 RESET Registers
      7. 8.6.7 DC Registers
      8. 8.6.8 PWM Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Program Procedure
      4. 9.2.4 Application Performance Plots
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.3.1 Program Procedure

When selecting data refresh Mode 1, outputs are refreshed instantly after data is received.

When selecting data refresh Mode 2 and 3, VSYNC signal is required for synchronized display. Programming flow is showed as Figure 9-2. To display full pixel of last frame, VSYNC pulse must be sent to the device after the end of last PWM. Time between two pulses tSYNC must be larger than the whole PWM time of all Dots tframe. Common selection like 60 Hz, 90 Hz, 120 Hz or even higher refresh frequency can be supported. High pulse width longer than tSYNC_H is required at the beginning of each VSYNC frame, and data must not be write to PWM registers during high pulse width.

GUID-3E9F909C-CEDF-4A37-A3E3-09A8D79FD059-low.svgFigure 9-2 Program Procedure