LP5912 500-mA Low-Noise, Low-IQ LDO
- SNVSA77D December 2015 – November 2016 LP5912
  
  PRODUCTION DATA.

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DATA SHEET

LP5912 500-mA Low-Noise, Low-IQ LDO

1 Features

Input Voltage Range: 1.6 V to 6.5 V
Output Voltage Range: 0.8 V to 5.5 V
Output Current up to 500 mA
Low Output-Voltage Noise: 12 µV_RMS Typical
PSRR at 1 kHz: 75 dB Typical
Output Voltage Tolerance (V_OUT ≥ 3.3 V): ±2%
Low I_Q (Enabled, No Load): 30 µA Typical
Low Dropout (V_OUT ≥ 3.3 V): 95 mV Typical at 500-mA Load
Stable With 1-µF Ceramic Input and Output Capacitors
Thermal-Overload and Short-Circuit Protection
Reverse Current Protection
No Noise Bypass Capacitor Required
Output Automatic Discharge for Fast Turnoff
Power-Good Output With 140-µs Typical Delay
Internal Soft-Start to Limit the In-rush Current
–40°C to +125°C Operating Junction Temperature Range

2 Applications

Camera Modules
Sensors
HiFi Audio Radio Transceivers
PLL/Synthesizer, Clocking
Medium-Current, Noise-Sensitive Applications

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3 Description

The LP5912 is low-noise LDO that can supply up to 500 mA of output current. Designed to meet the requirements of RF and analog circuits, the LP5912 device provides low noise, high PSRR, low quiescent current, and low line and load transient response. The LP5912 offers class-leading noise performance without a noise bypass capacitor and with the ability for remote output capacitance placement.

The device is designed to work with a 1-µF input and a 1-µF output ceramic capacitor (no separate noise bypass capacitor required).

This device is available with fixed output voltages from 0.8 V to 5.5 V in 25-mV steps. Contact Texas Instruments Sales for specific voltage option needs.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LP5912	WSON (6)	2.00 mm × 2.00 mm

For all available packages, see the Package Option Addendum (POA) at the end of this data sheet.

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Simplified Schematic

4 Revision History

Changes from C Revision (September 2016) to D Revision

Added package drawing Go

Changes from B Revision (June 2016) to C Revision

Changed wording of data sheet title Go
Changed wording of first sentence of DescriptionGo

Changes from A Revision (April 2016) to B Revision

Changed "linear regulator" to "LDO" on page 1 Go

5 Voltage Options

This device is capable of providing fixed output voltages from 0.8 V to 5.5 V in 25-mV steps. For all available package and voltage options, see the POA at the end of this datasheet. Contact Texas Instruments Sales for specific voltage option needs.

6 Pin Configuration and Functions

DRV Package

6-Pin WSON With Thermal Pad

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NUMBER	NAME	I/O	DESCRIPTION
1	OUT	O	Regulated output voltage
2	NC	—	No internal connection. Leave open, or connect to ground.
3	PG	O	Power-good indicator. Requires external pullup.
4	EN	I	Enable input. Logic high = device is ON, logic low = device is OFF, with internal 3-MΩ pulldown.
5	GND	G	Ground
6	IN	I	Unregulated input voltage
—	Exposed thermal pad	—	Connect to copper area under the package to improve thermal performance. The use of thermal vias to transfer heat to inner layers of the PCB is recommended. Connect the thermal pad to ground, or leave floating. Do not connect the thermal pad to any potential other than ground.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
V_IN	Input voltage	–0.3	7	V
V_OUT	Output voltage	–0.3	7	V
V_EN	Enable input voltage	-0.3	7	V
V_PG	Power Good (PG) pin OFF voltage	–0.3	7	V
T_J	Junction temperature		150	°C
P_D	Continuous power dissipation⁽³⁾	Internally Limited		W
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the GND pin.

(3) Internal thermal shutdown circuitry protects the device from permanent damage.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process..

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_IN	Input supply voltage	1.6	6.5	V
V_OUT	Output voltage	0.8	5.5
V_EN	Enable input voltage	0	V_IN
V_PG	PG pin OFF voltage	0	6.5
I_OUT	Output current	0	500	mA
T_J-MAX-OP	Operating junction temperature⁽²⁾	–40	125	°C

(1) All voltages are with respect to the GND pin.

(2) T_J-MAX-OP = (T_A(MAX) + (P_D(MAX) × R_θJA )).

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		LP5912	UNIT
		DRV (WSON)
		6 PINS
R_θJA	Junction-to-ambient thermal resistance, High-K⁽²⁾	71.2⁽³⁾	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	93.7	°C/W
R_θJB	Junction-to-board thermal resistance	40.7	°C/W
ψ_JT	Junction-to-top characterization parameter	2.5	°C/W
ψ_JB	Junction-to-board characterization parameter	41.1	°C/W
R_JC(bot)	Junction-to-case (bottom) thermal resistance	11.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(2) Thermal resistance value R_θJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.

(3) The PCB for the WSON (DRV) package R_θJA includes two (2) thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5.

7.5 Electrical Characteristics

V_IN = V_OUT(NOM) + 0.5 V or 1.6 V, whichever is greater; V_EN = 1.3 V, C_IN = 1 µF, C_OUT = 1 µF, I_OUT = 1 mA (unless otherwise stated).⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OUTPUT VOLTAGE
ΔV_OUT	Output voltage tolerance	For V_OUT(NOM) ≥ 3.3 V: V_OUT(NOM) + 0.5 V ≤ V_IN ≤ 6.5 V, I_OUT = 1 mA to 500 mA	–2%		2%
		For 1.1 V ≤ V_OUT(NOM) < 3.3 V: V_OUT(NOM) + 0.5 V ≤ V_IN ≤ 6.5 V, I_OUT = 1 mA to 500 mA	–3%		3%
		For V_OUT(NOM) < 1.1 V: 1.6 V ≤ V_IN ≤ 6.5 V, I_OUT = 1 mA to 500 mA	–3%		3%
	Line regulation	For V_OUT(NOM) ≥ 1.1V: V_OUT(NOM) + 0.5 V ≤ V_IN ≤ 6.5 V		0.8		%/V
	Line regulation	For V_OUT(NOM) < 1.1V : 1.6 V ≤ V_IN ≤ 6.5 V		0.8		%/V
	Load regulation	I_OUT = 1 mA to 500 mA		0.0022		%/mA
CURRENT LEVELS
I_SC	Short-circuit current limit	T_J = 25°C, see⁽⁴⁾	700	900	1100	mA
I_RO	Reverse leakage current⁽⁵⁾	V_EN = V_IN = 0 V, V_OUT= 5.5 V		10	150	µA
I_Q	Quiescent current⁽⁶⁾	V_EN = 1.3 V, I_OUT = 0 mA		30	55	µA
I_Q	Quiescent current⁽⁶⁾	V_EN = 1.3 V, I_OUT = 500 mA		400	600	µA
I_Q(SD)	Quiescent current, shutdown mode⁽⁶⁾	V_EN = 0 V –40°C ≤ T_J ≤ 85°C		0.2	1.5	µA
I_Q(SD)	Quiescent current, shutdown mode⁽⁶⁾	V_EN = 0 V		0.2	5	µA
I_G	Ground current⁽⁷⁾	V_EN = 1.3 V, I_OUT = 0 mA		35		µA
VDO DROPOUT VOLTAGE
V_DO	Dropout voltage⁽⁸⁾	I_OUT = 500 mA, 1.6 V ≤ V_OUT(NOM) < 3.3 V		170	250	mV
V_DO	Dropout voltage⁽⁸⁾	I_OUT = 500 mA, 3.3 V ≤ V_OUT(NOM) ≤ 5.5 V		95	180	mV
VIN to VOUT RIPPLE REJECTION
PSRR	Power Supply Rejection Ratio⁽¹⁰⁾	ƒ = 100 Hz, V_OUT ≥ 1.1 V, I_OUT = 20 mA		80		dB
		ƒ = 1 kHz, V_OUT ≥ 1.1 V, I_OUT = 20 mA		75
		ƒ = 10 kHz, V_OUT ≥ 1.1 V, I_OUT = 20 mA		65
		ƒ = 100 kHz, V_OUT ≥ 1.1 V, I_OUT = 20 mA		40
		ƒ = 100 Hz, 0.8 V < V_OUT < 1.1 V, I_OUT = 20 mA		65
		ƒ = 1 kHz, 0.8 V < V_OUT < 1.1 V, I_OUT = 20 mA		65
		ƒ = 10 kHz, 0.8 V < V_OUT < 1.1 V, I_OUT = 20 mA		65
		ƒ = 100 kHz, 0.8 V < V_OUT < 1.1 V, I_OUT = 20 mA		40
OUTPUT NOISE VOLTAGE
e_N	Noise voltage	I_OUT = 1 mA, BW = 10 Hz to 100 kHz		12		µV_RMS
e_N	Noise voltage	I_OUT = 500 mA, BW = 10 Hz to 100 kHz		12		µV_RMS
THERMAL SHUTDOWN
T_SD	Thermal shutdown temperature			160		°C
T_HYS	Thermal shutdown hysteresis			15		°C
LOGIC INPUT THRESHOLDS
V_EN(OFF)	OFF Threshold	V_IN = 1.6 V to 6.5 V V_EN falling until device is disabled			0.3	V
V_EN(ON)	ON Threshold	1.6 V ≤ V_IN≤ 6.5 V V_EN rising until device is enabled	1.3			V
I_EN	Input current at EN pin⁽⁹⁾	V_EN = 6.5 V, V_IN = 6.5 V		2.5		µA
I_EN	Input current at EN pin⁽⁹⁾	V_EN = 0 V, V_IN = 3.3 V		0.001		µA
PG_HTH	PG high threshold (% of nominal V_OUT)			94%
PG_LTH	PG low threshold (% of nominal V_OUT)			90%
V_OL(PG)	PG pin low-level output voltage	V_OUT < PG_LTH, sink current = 1 mA			100	mV
I_lKG(PG)	PG pin leakage current	V_OUT < PG_HTH, V_PG = 6.5 V			1	µA
t_PGD	PG delay time	Time from V_OUT > PG threshold to PG toggling		140		µs
TRANSITION CHARACTERISTICS
ΔV_OUT	Line transients⁽¹⁰⁾	For V_IN ↑ and V_OUT(NOM) ≥ 1.1 V: V_IN = (V_OUT(NOM) + 0.5 V) to (V_OUT(NOM) + 1.1 V) V_IN t_rise = 30 µs			1	mV
		For V_IN ↑ and V_OUT(NOM) < 1.1 V: V_IN = 1.6 V to 2.2 V V_IN t_rise = 30 µs			1
		For V_IN ↓ and V_OUT(NOM) ≥ 1.1 V V_IN = (V_OUT(NOM) + 1.1 V) to (V_OUT(NOM) + 0.5 V) V_IN t_fall = 30 µs	–1
		For V_IN ↓ and V_OUT(NOM) < 1.1 V: V_IN = 2.2 V to 1.6 V V_IN t_fall = 30 µs	–1
	Load transients⁽¹⁰⁾	I_OUT = 5 mA to 500 mA I_OUT t_rise = 10 µs	–45			mV
	Load transients⁽¹⁰⁾	I_OUT = 500 mA to 5 mA I_OUT t_fall = 10 µs			45	mV
	Overshoot on start-up⁽¹⁰⁾	Stated as a percentage of V_OUT(NOM)			5%
t_ON	Turnon time	Time from V_EN > V_EN(ON) to V_OUT = 95% of V_OUT(NOM)		200		µs
OUTPUT AUTO DISCHARGE RATE
R_AD	Output discharge pull-down resistance	V_EN = 0 V, V_IN = 3.6 V		100		Ω

(1) All voltages are with respect to the device GND pin, unless otherwise stated.

(2) Minimum and maximum limits are ensured through test, design, or statistical correlation over the junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated. Typical values represent the most likely parametric norm at T_A = 25°C, and are provided for reference purposes only.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP = 125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the part/package in the application (R_θJA), as given by the following equation: T_A-MAX = T_J-MAX-OP – (R_θJA × P_D-MAX).

(4) Short-circuit current (I_SC) is equivalent to current limit. To minimize thermal effects during testing, I_SC is measured with V_OUT pulled to 100 mV below its nominal voltage.

(5) Reverse current (I_RO) is measured at the IN pin.

(6) Quiescent current is defined here as the difference in current between the input voltage source and the load at V_OUT.

(7) Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device.

(8) Dropout voltage (V_DO) is the voltage difference between the input and the output at which the output voltage drops to 150 mV below its nominal value when V_IN = V_OUT + 0.5 V. Dropout voltage is not a valid condition for output voltages less than 1.6 V as compliance with the minimum operating voltage requirement cannot be assured.

(9) There is a 3-MΩ pulldown resistor between the EN pin and GND pin on the device.

(10) This specification is ensured by design.

7.6 Output and Input Capacitors

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN⁽¹⁾	TYP	MAX	UNIT
C_IN	Input capacitance⁽²⁾	Capacitance for stability	0.7	1		µF
C_OUT	Output capacitance⁽²⁾	Capacitance for stability	0.7	1	10	µF
ESR	Output voltage⁽²⁾		5		500	mΩ

(1) The minimum capacitance must be greater than 0.5 μF over full range of operating conditions. The capacitor tolerance must be 30% or better over the full temperature range. The full range of operating conditions for the capacitor in the application must be considered during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended however capacitor types X5R, Y5V, and Z5U may be used with consideration of the application conditions.

(2) This specification is verified by design.

8 Typical Characteristics

Unless otherwise stated: V_IN = V_OUT + 0.5 V, V_EN = V_IN, I_OUT = 1 mA, C_IN = 1 µF, C_OUT = 1 µF, T_J = 25°C, unless otherwise stated.

Figure 1. V_EN Thresholds vs Input Voltage

Figure 3. LP5912-1.8 Output Voltage, V_PG vs Input Voltage

V_IN = 0 V to 1.6 V		I_OUT = 1 mA

Figure 5. LP5912-0.9 Power Up

V_IN = 0 V to 2.3 V		I_OUT = 1 mA

Figure 7. LP5912-1.8 Power Up

V_IN = 0 V to 3.8 V		I_OUT = 1 mA

Figure 9. LP5912-3.3 Power Up

I_OUT = 0 mA

Figure 11. LP5912-0.9 I_Q (No Load) vs V_IN

I_OUT = 0 mA

Figure 13. LP5912-3.3 I_Q (No Load) vs V_IN

V_EN = 0 V

Figure 15. LP5912-1.8 I_Q_(SD) vs V_IN

V_IN = 1.6 V

Figure 17. LP5912-0.9 I_GND vs I_OUT

Figure 19. LP5912-3.3 I_GND vs I_OUT

V_IN = 1.6 V

Figure 21. LP5912-0.9 PSRR vs Frequency

Figure 23. LP5912-1.8 PSRR vs Frequency

Figure 25. LP5912-3.3 PSRR vs Frequency

V_IN = 2.2 V to 1.6 V		t_fall = 30 µs

Figure 27. LP5912-0.9 Line Transient

V_IN = 2.9 V to 2.3 V		t_fall = 30 µs

Figure 29. LP5912-1.8 Line Transient

V_IN = 4.4 V to 3.8 V		t_fall = 30 µs

Figure 31. LP5912-3.3 Line Transient

V_IN = 1.6 V	I_OUT = 500 mA to 5 mA	t_fall = 10 µs

Figure 33. LP5912-0.9 Load Transient Response

I_OUT = 500 mA to 5 mA		t_fall = 10 µs

Figure 35. LP5912-1.8 Load Transient Response

I_OUT = 500 mA to 5 mA		t_fall = 10 µs

Figure 37. LP5912-3.3 Load Transient Response

I_OUT = 0 mA

C_OUT = 1 µF

Figure 39. LP5912-1.8 V_OUT vs V_EN(OFF)

I_OUT = 1 mA

C_OUT = 1 µF

Figure 41. LP5912-1.8 V_OUT vs V_EN(OFF)

I_OUT = 500 mA

C_OUT = 1 µF

Figure 43. LP5912-1.8 V_OUT vs V_EN(OFF)

Figure 45. LP5912-3.3 Dropout Voltage (V_DO) vs I_OUT

Figure 47. LP5912-1.8 Noise vs Frequency

I_OUT = 0 mA (No Load)

Figure 49. LP5912-3.3 Turnon Time vs Junction Temperature

C_IN = Open	I_OUT = 1 mA	C_OUT = 1 µF

Figure 51. LP5912-3.3 In-Rush Current

	C_IN = Open	I_OUT = 1 mA	C_OUT = 10 µF

Figure 53. LP5912-3.3 In-Rush Current

Figure 2. LP5912-0.9 Output Voltage, V_PG vs Input Voltage

Figure 4. LP5912-3.3 Output Voltage, V_PG vs Input Voltage

V_IN = 0 V to 1.6 V		I_OUT = 500 mA

Figure 6. LP5912-0.9 Power Up

V_IN = 0 V to 2.3 V		I_OUT = 500 mA

Figure 8. LP5912-1.8 Power Up

V_IN = 0 V to 3.8 V		I_OUT = 500 mA

Figure 10. LP5912-3.3 Power Up

I_OUT = 0 mA

Figure 12. LP5912-1.8 I_Q (No Load) vs V_IN

V_EN = 0 V

Figure 14. LP5912-0.9 I_Q_(SD) vs V_IN

V_EN = 0 V

Figure 16. LP5912-3.3 I_Q_(SD) vs V_IN

Figure 18. LP5912-1.8 I_GND vs I_OUT

V_IN = 1.6 V		I_OUT = 20 mA

Figure 20. LP5912-0.9 PSRR vs Frequency

I_OUT = 20 mA

Figure 22. LP5912-1.8 PSRR vs Frequency

I_OUT = 20 mA

Figure 24. LP5912-3.3 PSRR vs Frequency

V_IN = 1.6 V to 2.2 V		t_rise = 30 µs

Figure 26. LP5912-0.9 Line Transient

V_IN = 2.3 V to 2.9 V		t_rise = 30 µs

Figure 28. LP5912-1.8 Line Transient

V_IN = 3.8 V to 4.4 V		t_rise = 30 µs

Figure 30. LP5912-3.3 Line Transient

V_IN = 1.6 V	I_OUT = 5 mA to 500 mA	t_rise = 10 µs

Figure 32. LP5912-0.9 Load Transient Response

I_OUT = 5 mA to 500 mA		t_rise = 10 µs

Figure 34. LP5912-1.8 Load Transient Response

I_OUT = 5 mA to 500 mA		t_rise = 10 µs

Figure 36. LP5912-3.3 Load Transient Response

I_OUT = 0 mA		C_OUT = 1 µF

Figure 38. LP5912-1.8 V_OUT vs V_EN(ON)

I_OUT = 1 mA

C_OUT = 1 µF

Figure 40. LP5912-1.8 V_OUT vs V_EN(ON)

I_OUT = 500 mA

C_OUT = 1 µF

Figure 42. LP5912-1.8 V_OUT vs V_EN(ON)

Figure 44. LP5912-1.8 Dropout Voltage (V_DO) vs I_OUT

V_IN = 1.6 V

Figure 46. LP5912-0.9 Noise vs Frequency

Figure 48. LP5912-3.3 Noise vs Frequency

C_IN = Open	I_OUT = 500 mA	C_OUT = 1 µF

Figure 50. LP5912-3.3 In-Rush Current

C_IN = Open	I_OUT = 500 mA	C_OUT = 10 µF

Figure 52. LP5912-3.3 In-Rush Current