JAJSCR1 November   2016 LP5922

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Input and Output Capacitors
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage
      2. 7.3.2 Enable
      3. 7.3.3 Output Automatic Discharge
      4. 7.3.4 Programmable Soft Start and Noise Reduction
      5. 7.3.5 Internal Current Limit
      6. 7.3.6 Thermal Overload Protection
      7. 7.3.7 Power Good Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable (EN)
      2. 7.4.2 Undervoltage Lockout (UVLO)
      3. 7.4.3 Minimum Operating Input Voltage
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
        2. 8.2.2.2 Input Capacitor, CIN
        3. 8.2.2.3 Output Capacitor, COUT
        4. 8.2.2.4 Soft-Start and Noise-Reduction Capacitor, CSS/NR
        5. 8.2.2.5 Feed-Forward Capacitor, CFF
        6. 8.2.2.6 No-Load Stability
        7. 8.2.2.7 Power Dissipation
        8. 8.2.2.8 Estimating Junction Temperature
        9. 8.2.2.9 Recommended Continuous Operating Area
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

The dynamic performance of the LP5922 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5922.

Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5922 device, and as close as is practical to the package. The ground connections for CIN and COUT must be back to the LP5922 GND pin using as wide and as short of a copper trace as is practical.

Avoid connections using long trace lengths, narrow trace widths, or connections through vias. These add parasitic inductances and resistance that results in inferior performance especially during transient conditions

10.2 Layout Example

LP5922 layout_snvsag0.gif Figure 25. LP5922 Typical Layout