7.3.1 Output Voltage

The LP5922 output voltage can be set to any value from 0.5 V to 5 V using two external resistors shown as R_UPPER and R_LOWER in Figure 15. The value for the R_LOWER should be less than or equal to 100 kΩ for good loop compensation. R_UPPER can be selected for a given V_OUT using Equation 1:

Equation 1.

where

• V_FB = 0.5 V

7.3.2 Enable

The LP5922 EN pin is internally held low by a 2-MΩ resistor to GND. The EN pin voltage must be higher than the V_IH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage must be lower than the VIL threshold to ensure that the device is fully disabled and the automatic output discharge is activated.

7.3.3 Output Automatic Discharge

The LP5922 output employs an internal 400-Ω (typical) pulldown resistance to discharge the output capacitor when the EN pin is low, and the device is disabled.

7.3.4 Programmable Soft Start and Noise Reduction

The output voltage of LP5922 ramps up linearly in a constant slew rate until reaching the target regulating voltage after a stable V_IN (greater than V_OUT + V_DO) is supplied and EN pin is pulled high. The slew rate of V_OUT ramping is programmable by an external capacitor on the SS/NR pin; therefore, the duration for soft-start period is programmable as well. Once the LP5922 is enabled, the SS/NR pin sources a constant 6-µA current to charge the external C_SS/NR capacitor until the voltage at the SS/NR pin reaches 98% of the internal reference voltage (V_REF) of 500 mV typical. The final 2% of C_SS/NR charge is determined by a RC time constant. During the soft-start period, the current flowing into the IN pin primarily consists of the sum of the load current at the LDO output and the charging current into the output capacitor. The soft-start period can be calculated by Equation 2:

Equation 2.

where

• V_FB = 0.5 V - this is the voltage that C_SS/NR charges to;
• C_SS/NR is the value of the capacitor connected between the SS/NR pin and ground; and
• I_SS = 6.2 µA is the typical charging current to the SS/NR pin during start-up period.

The recommended value for C_SS/NR is 100 nF or larger. Equation 2 is most accurate for these values. The C_SS/NR capacitor is also the filter capacitor for internal reference for noise reduction purpose. An integrated resistor and the C_SS/NR capacitor structure a RC low-pass filter to remove the noise on the internal reference voltage.

7.3.5 Internal Current Limit

The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The LDO is not designed to operate in a steady-state current limit. During a current-limit event, the LDO sources constant current. Therefore, the output voltage falls when load impedance decreases. Note also that if a current limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting in a thermal shutdown of the output.

7.3.6 Thermal Overload Protection

Thermal shutdown disables the output when the junction temperature rises to T_SD level, which allows the device to cool. When the junction temperature cools by ΔT_SD, the output circuitry enables. Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a result of overheating.

The internal protection circuitry of the LP5922 is designed to protect against thermal overload conditions. The circuitry is not intended to replace proper heat sinking. Continuously running the LP5922 into thermal shutdown degrades device reliability.

7.3.7 Power Good Output

The LP5922 has a Power-Good function that works by toggling the state of the PG output pin. When the output voltage falls below the PG threshold voltage (PG_LTH), the PG pin open-drain output engages (low impedance to GND). When the output voltage rises above the PG threshold voltage (PG_HTH), the PG pin becomes high-impedance. By connecting a pullup resistor to an external supply, any downstream device can receive PG as a logic signal. User must make sure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices; use a pullup resistor from 10 kΩ to 100 kΩ for best results.

In Power-Good function, the PG output pin pulled high immediatelly after output voltage rises above the PG threshold voltage.

7.4.1 Enable (EN)

The LP5922 enable (EN) pin is internally held low by a 2-MΩ resistor to GND. If the EN pin is open the output is OFF. The EN pin voltage must be higher than the V_IH threshold to ensure that the device is fully enabled under all operating conditions. When the EN pin is pulled low, and the output is disabled, the output automatic discharge circuit is activated. Any charge on the OUT pin is discharged to GND through the internal pulldown resistance.

7.4.2 Undervoltage Lockout (UVLO)

The LP5922 incorporates UVLO. The UVLO circuit monitors the input voltage and keeps the LP5922 disabled while a rising V_IN is less than 1.2 V (typical). The rising UVLO threshold is approximately 100 mV below the recommended minimum operating V_IN of 1.3 V.

7.4.3 Minimum Operating Input Voltage

The LP5922 internal circuit is not fully functional until V_IN is at least 1.3 V. The output voltage is not regulated until V_IN has reached at least the greater of 1.3 V or (V_OUT + V_DO).