JAJSG71A
June 2019 – June 2021
LP8733-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
I2C Serial Bus Timing Parameters
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
DC/DC Converters
7.3.1.1
Overview
7.3.1.2
Dual-Phase Operation and Phase-Adding/Shedding
7.3.1.3
Transition Between PWM and PFM Modes
7.3.1.4
Dual-Phase Switcher Configurations
7.3.1.5
Buck Converter Load Current Measurement
7.3.1.6
Spread-Spectrum Mode
7.3.2
Sync Clock Functionality
7.3.3
Low-Dropout Linear Regulators (LDOs)
7.3.4
Power-Up
7.3.5
Regulator Control
7.3.5.1
Enabling and Disabling Regulators
7.3.5.2
Changing Output Voltage
7.3.6
Enable and Disable Sequences
7.3.7
Device Reset Scenarios
7.3.8
Diagnosis and Protection Features
7.3.8.1
Power-Good Information (PGOOD pin)
7.3.8.1.1
PGOOD Pin Gated Mode
7.3.8.1.2
PGOOD Pin Continuous Mode
7.3.8.1.3
PGOOD Pin Inactive Mode
7.3.8.2
Warnings for Diagnosis (Interrupt)
7.3.8.2.1
Output Power Limit
7.3.8.2.2
Thermal Warning
7.3.8.3
Protection (Regulator Disable)
7.3.8.3.1
Short-Circuit and Overload Protection
7.3.8.3.2
Overvoltage Protection
7.3.8.3.3
Thermal Shutdown
7.3.8.4
Fault (Power Down)
7.3.8.4.1
Undervoltage Lockout
7.3.9
Operation of the GPO Signals
7.3.10
Digital Signal Filtering
7.4
Device Functional Modes
7.4.1
Modes of Operation
7.5
Programming
7.5.1
I2C-Compatible Interface
7.5.1.1
Data Validity
7.5.1.2
Start and Stop Conditions
7.5.1.3
Transferring Data
7.5.1.4
I2C-Compatible Chip Address
7.5.1.5
Auto-Increment Feature
7.6
Register Maps
7.6.1
Register Descriptions
7.6.1.1
DEV_REV
7.6.1.2
OTP_REV
7.6.1.3
BUCK0_CTRL_1
7.6.1.4
BUCK0_CTRL_2
7.6.1.5
BUCK1_CTRL_1
7.6.1.6
BUCK1_CTRL_2
7.6.1.7
BUCK0_VOUT
7.6.1.8
BUCK1_VOUT
7.6.1.9
LDO0_CTRL
7.6.1.10
LDO1_CTRL
7.6.1.11
LDO0_VOUT
7.6.1.12
LDO1_VOUT
7.6.1.13
BUCK0_DELAY
7.6.1.14
BUCK1_DELAY
7.6.1.15
LDO0_DELAY
7.6.1.16
LDO1_DELAY
7.6.1.17
GPO_DELAY
7.6.1.18
GPO2_DELAY
7.6.1.19
GPO_CTRL
7.6.1.20
CONFIG
7.6.1.21
PLL_CTRL
7.6.1.22
PGOOD_CTRL_1
7.6.1.23
PGOOD_CTRL_2
7.6.1.24
PG_FAULT
7.6.1.25
RESET
7.6.1.26
INT_TOP_1
7.6.1.27
INT_TOP_2
7.6.1.28
INT_BUCK
7.6.1.29
INT_LDO
7.6.1.30
TOP_STAT
7.6.1.31
BUCK_STAT
7.6.1.32
LDO_STAT
7.6.1.33
TOP_MASK_1
7.6.1.34
TOP_MASK_2
7.6.1.35
BUCK_MASK
7.6.1.36
LDO_MASK
7.6.1.37
SEL_I_LOAD
7.6.1.38
I_LOAD_2
7.6.1.39
I_LOAD_1
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Design Requirements
8.2.1.1
Inductor Selection
8.2.1.2
Buck Input Capacitor Selection
8.2.1.3
Buck Output Capacitor Selection
8.2.1.4
LDO Input Capacitor Selection
8.2.1.5
LDO Output Capacitor Selection
8.2.1.6
Current Limit vs. Maximum Output Current
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.2
Receiving Notification of Documentation Updates
11.3
サポート・リソース
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RHD|28
MPQF133F
サーマルパッド・メカニカル・データ
RHD|28
QFND560A
発注情報
jajsg71a_oa
jajsg71a_pm