SNVSB23 Data sheet

SNVSB23 March 2018 LP87521-Q1 , LP87522-Q1 , LP87523-Q1 , LP87524-Q1 , LP87525-Q1

PRODUCTION DATA.

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

RNF|26

サーマルパッド・メカニカル・データ

発注情報

8.3.2 Sync Clock Functionality

The LP8752x-Q1 device contains a CLKIN input to synchronize the switching clock of the buck regulator with the external clock. The block diagram of the clocking and PLL module is shown in Figure 13. Depending on the PLL_MODE[1:0] bits (in PLL_CTRL register) and the external clock availability, the external clock is selected, and interrupt is generated, as shown in Table 2. The interrupt can be masked with SYNC_CLK_MASK bit in TOP_MASK1 register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0] bits (in PLL_CTRL register), and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be inside accuracy limits (–30%/+10%) for valid clock detection.

The NO_SYNC_CLK interrupt (in INT_TOP1 register) is also generated in cases when the external clock is expected but it is not available. These cases are start-up (read OTP-to-STANDBY transition) when PLL_MODE[1:0] = 01 and regulator enable (STANDBY-to-ACTIVE transition) when PLL_MODE[1:0] = 10.

LP87521-Q1 LP87522-Q1 LP87523-Q1 LP87524-Q1 LP87525-Q1 Clock_PLL.gif

Figure 13. Clock and PLL Module

Table 2. PLL Operation

DEVICE OPERATION MODE	PLL_MODE[1:0]	PLL AND CLOCK DETECTOR STATE	INTERRUPT FOR EXTERNAL CLOCK	CLOCK
STANDBY	0h	Disabled	No	Internal RC
ACTIVE	0h	Disabled	No	Internal RC
STANDBY	1h	Enabled	When external clock appears or disappears	Automatic change to external clock when available
ACTIVE	1h	Enabled	When external clock appears or disappears	Automatic change to external clock when available
STANDBY	2h	Disabled	No	Internal RC
ACTIVE	2h	Enabled	When external clock appears or disappears	Automatic change to external clock when available
STANDBY	3h	Reserved
ACTIVE	3h	Reserved