JAJSE47B April   2017  – December 2018 LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     概略回路図
  3. 3 概要
    1.     効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 概要（続き）
    1.     Device Images
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Descriptions
      1. 8.3.1 DC-DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Transition Between PWM and PFM Modes
        3. 8.3.1.3 Buck Converter Load-Current Measurement
        4. 8.3.1.4 Spread-Spectrum Mode
      2. 8.3.2 Sync Clock Functionality
      3. 8.3.3 Power-Up
      4. 8.3.4 Regulator Control
        1. 8.3.4.1 Enabling and Disabling Regulators
        2. 8.3.4.2 Changing Output Voltage
      5. 8.3.5 Enable and Disable Sequences
      6. 8.3.6 Device Reset Scenarios
      7. 8.3.7 Diagnosis and Protection Features
        1. 8.3.7.1 Power-Good Information (PGOOD pin)
        2. 8.3.7.2 Warnings for Diagnosis (Interrupt)
          1. 8.3.7.2.1 Output Power Limit
          2. 8.3.7.2.2 Thermal Warning
        3. 8.3.7.3 Protection (Regulator Disable)
          1. 8.3.7.3.1 Short-Circuit and Overload Protection
          2. 8.3.7.3.2 Overvoltage Protection
          3. 8.3.7.3.3 Thermal Shutdown
        4. 8.3.7.4 Fault (Power Down)
          1. 8.3.7.4.1 Undervoltage Lockout
      8. 8.3.8 GPIO Signal Operation
      9. 8.3.9 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto-Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1  OTP_REV
        2. 8.6.1.2  BUCK0_CTRL1
        3. 8.6.1.3  BUCK1_CTRL1
        4. 8.6.1.4  BUCK2_CTRL1
        5. 8.6.1.5  BUCK3_CTRL1
        6. 8.6.1.6  BUCK0_VOUT
        7. 8.6.1.7  BUCK0_FLOOR_VOUT
        8. 8.6.1.8  BUCK1_VOUT
        9. 8.6.1.9  BUCK1_FLOOR_VOUT
        10. 8.6.1.10 BUCK2_VOUT
        11. 8.6.1.11 BUCK2_FLOOR_VOUT
        12. 8.6.1.12 BUCK3_VOUT
        13. 8.6.1.13 BUCK3_FLOOR_VOUT
        14. 8.6.1.14 BUCK0_DELAY
        15. 8.6.1.15 BUCK1_DELAY
        16. 8.6.1.16 BUCK2_DELAY
        17. 8.6.1.17 BUCK3_DELAY
        18. 8.6.1.18 GPIO2_DELAY
        19. 8.6.1.19 GPIO3_DELAY
        20. 8.6.1.20 RESET
        21. 8.6.1.21 CONFIG
        22. 8.6.1.22 INT_TOP1
        23. 8.6.1.23 INT_TOP2
        24. 8.6.1.24 INT_BUCK_0_1
        25. 8.6.1.25 INT_BUCK_2_3
        26. 8.6.1.26 TOP_STAT
        27. 8.6.1.27 BUCK_0_1_STAT
        28. 8.6.1.28 BUCK_2_3_STAT
        29. 8.6.1.29 TOP_MASK1
        30. 8.6.1.30 TOP_MASK2
        31. 8.6.1.31 BUCK_0_1_MASK
        32. 8.6.1.32 BUCK_2_3_MASK
        33. 8.6.1.33 SEL_I_LOAD
        34. 8.6.1.34 I_LOAD_2
        35. 8.6.1.35 I_LOAD_1
        36. 8.6.1.36 PGOOD_CTRL1
        37. 8.6.1.37 PGOOD_CTRL2
        38. 8.6.1.38 PGOOD_FLT
        39. 8.6.1.39 PLL_CTRL
        40. 8.6.1.40 PIN_FUNCTION
        41. 8.6.1.41 GPIO_CONFIG
        42. 8.6.1.42 GPIO_IN
        43. 8.6.1.43 GPIO_OUT
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Inductor Selection
        2. 9.2.1.2 Input Capacitor Selection
        3. 9.2.1.3 Output Capacitor Selection
        4. 9.2.1.4 Snubber Components
        5. 9.2.1.5 Supply Filtering Components
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RNF|26
サーマルパッド・メカニカル・データ
発注情報

9.2.3 Application Curves

Measurements are done using typical application set up with connections shown in Figure 22 (snubber components included when VIN > 4 V). Graphs may not reflect the OTP default settings. Unless otherwise specified: VIN = 3.7 V, VOUT = 1 V, V(NRST) = 1.8 V, TA = 25°C, ƒSW = 4 MHz, L = 0.47 µH (TOKO DFE252012PD-R47M), COUT = 22 µF / phase, and CPOL = 22 µF / phase. Measurements are done using connections in the Typical Application.

LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D923_LP8756.gif
VOUT = 1.8 V
Figure 23. Efficiency in PFM/PWM Mode
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D925_LP8756.gif
VIN = 5 V
Figure 25. Efficiency in Forced-PWM Mode
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D027_LP8756.gifFigure 27. Output Voltage vs Load Current in PFM/PWM Mode
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D036_LP8756.gif
Load = 1 A (PWM) and 0.1 A (PFM)
Figure 29. Output Voltage vs Temperature
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D906_LP8756.gif
RLOAD = 1 Ω
Figure 31. Start-Up With EN1, Forced PWM
(1-Phase Output)
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D999_LP8756.gif
IOUT = 10 mA
Figure 33. Output Voltage Ripple, PFM Mode
(1-Phase Output)
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D300_SNVSAW2.gif
VOUT = 1 V No load RBW/VBW = 10 Hz
Figure 35. Output Voltage Ripple Spectrum, Forced-PWM Mode. COUT = 22 µF, ferrite BLM18KG121TH1D, CPOL = 10 µF + 0.22 µF.
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D996_LP8756.gif
Figure 37. Transient from PWM-to-PFM Mode
(1-Phase Output)
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D994_LP8756.gif
IOUT = 0.1 A → 2 A → 0.1 A TR = TF = 1 µs
Figure 39. Transient Load Step Response, Forced-PWM Mode (1-Phase Output)
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D364_LP8752.gif
Figure 41. VOUT Transition from 1.4 V to 0.6 V
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D924_LP8756.gif
VIN = 3.3 V
Figure 24. Efficiency in Forced-PWM Mode
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D026_LP8756.gif
Figure 26. Output Voltage vs Load Current in Forced-PWM Mode
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D028_LP8756.gif
VOUT = 1 V Load = 1 A
Figure 28. Output Voltage vs Input Voltage in PWM Mode
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D905_LP8756.gif
IOUT = 0 A
Figure 30. Start-Up With EN1, Forced PWM
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D907_LP8756.gif
RLOAD = 1 Ω
Figure 32. Shutdown With EN1, Forced PWM
(1-Phase Output)
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D998_LP8756.gif
IOUT = 200 mA
Figure 34. Output Voltage Ripple, Forced-PWM Mode
(1-Phase Output)
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D997_LP8756.gif
Figure 36. Transient from PFM-to-PWM Mode
(1-Phase Output)
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D995_LP8756.gif
IOUT = 0.1 A → 2 A → 0.1 A TR = TF = 1 µs
Figure 38. Transient Load Step Response, AUTO Mode
(1-Phase Output)
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D365_LP8752.gif
Figure 40. VOUT Transition from 0.6 V to 1.4 V
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 D098_LP8756.gif
Figure 42. Start-up With Short on Output (1-Phase Output)