JAJSE47 データシート

JAJSE47B April 2017 – December 2018 LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1

PRODUCTION DATA.

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

RNF|26

サーマルパッド・メカニカル・データ

発注情報

8.6.1 Register Descriptions

The LP87524B/J/P-Q1 is controlled by a set of registers through the I²C-compatible interface. The device registers, their addresses, and their abbreviations are listed in Table 9. A more detailed description is given in the OTP_REV to GPIO_OUT sections.

The asterisk (*) marking indicates register bits which are updated from OTP memory during READ OTP state.

NOTE

This register map describes the default values read from OTP memory for a device with orderable code of LP87524BRNFRQ1, LP87524JRNFRQ1 and LP87524PRNFRQ1. For other LP8752x versions the default values read from OTP memory can be different.

Table 9. Summary of LP87524B/J/P-Q1 Control Registers

Addr	Register	Read / Write	D7	D6	D5	D4	D3	D2	D1	D0
0x01	OTP_REV	R	OTP_ID[7:0]
0x02	BUCK0_ CTRL1	R/W	EN_BUCK0	EN_PIN_ CTRL0	BUCK0_EN_PIN SELECT[1:0]		EN_ROOF _FLOOR0	EN_RDIS0	BUCK0_ FPWM	Reserved
0x04	BUCK1_ CTRL1	R/W	EN_BUCK1	EN_PIN_ CTRL1	BUCK1_EN_PIN SELECT[1:0]		EN_ROOF _FLOOR1	EN_RDIS1	BUCK1_ FPWM	Reserved
0x06	BUCK2_ CTRL1	R/W	EN_BUCK2	EN_PIN_ CTRL2	BUCK2_EN_PIN SELECT[1:0]		EN_ROOF _FLOOR2	EN_RDIS2	BUCK2_ FPWM	Reserved
0x08	BUCK3_ CTRL1	R/W	EN_BUCK3	EN_PIN_ CTRL3	BUCK3_EN_PIN SELECT[1:0]		EN_ROOF _FLOOR3	EN_RDIS3	BUCK3_ FPWM	Reserved
0x0A	BUCK0_ VOUT	R/W	BUCK0_VSET[7:0]
0x0B	BUCK0_ FLOOR_ VOUT	R/W	BUCK0_FLOOR_VSET[7:0]
0x0C	BUCK1_ VOUT	R/W	BUCK1_VSET[7:0]
0x0D	BUCK1_ FLOOR_ VOUT	R/W	BUCK1_FLOOR_VSET[7:0]
0x0E	BUCK2_ VOUT	R/W	BUCK2_VSET[7:0]
0x0F	BUCK2_ FLOOR_ VOUT	R/W	BUCK2_FLOOR_VSET[7:0]
0x10	BUCK3_ VOUT	R/W	BUCK3_VSET[7:0]
0x11	BUCK3_ FLOOR_ VOUT	R/W	BUCK3_FLOOR_VSET[7:0]
0x12	BUCK0_ DELAY	R/W	BUCK0_SHUTDOWN_DELAY[3:0]				BUCK0_STARTUP_DELAY[3:0]
0x13	BUCK1_ DELAY	R/W	BUCK1_SHUTDOWN_DELAY[3:0]				BUCK1_STARTUP_DELAY[3:0]
0x14	BUCK2_ DELAY	R/W	BUCK2_SHUTDOWN_DELAY[3:0]				BUCK2_STARTUP_DELAY[3:0]
0x15	BUCK3_ DELAY	R/W	BUCK3_SHUTDOWN_DELAY[3:0]				BUCK3_STARTUP_DELAY[3:0]
0x16	GPIO2_ DELAY	R/W	GPIO2_SHUTDOWN_DELAY[3:0]				GPIO2_STARTUP_DELAY[3:0]
0x17	GPIO3_ DELAY	R/W	GPIO3_SHUTDOWN_DELAY[3:0]				GPIO3_STARTUP_DELAY[3:0]
0x18	RESET	R/W	Reserved							SW_ RESET
0x19	CONFIG	R/W	DOUBLE_DELAY	CLKIN_PD	Reserved	EN3_PD	TDIE _WARN _LEVEL	EN2_PD	EN1_PD	Reserved
0x1A	INT_TOP1	R/W	Reserved	INT_ BUCK23	INT_ BUCK01	NO_SYNC _CLK	TDIE_SD	TDIE_ WARN	INT_ OVP	I_LOAD_ READY
0x1B	INT_TOP2	R/W	Reserved							RESET_ REG
0x1C	INT_BUCK_0_1	R/W	Reserved	BUCK1_ PG_INT	BUCK1_ SC_INT	BUCK1_ ILIM_INT	Reserved	BUCK0_ PG_INT	BUCK0_ SC_INT	BUCK0_ ILIM_INT
0x1D	INT_BUCK_2_3	R/W	Reserved	BUCK3_ PG_INT	BUCK3_ SC_INT	BUCK3_ ILIM_INT	Reserved	BUCK2_ PG_INT	BUCK2_ SC_INT	BUCK2_ ILIM_INT
0x1E	TOP_ STAT	R	Reserved			SYNC_CLK _STAT	TDIE_SD _STAT	TDIE_ WARN_ STAT	OVP_ STAT	Reserved
0x1F	BUCK_0_1_STAT	R	BUCK1_ STAT	BUCK1_ PG_STAT	Reserved	BUCK1_ ILIM_ STAT	BUCK0_ STAT	BUCK0_ PG_STAT	Reserved	BUCK0_ ILIM_ STAT
0x20	BUCK_2_3_STAT	R	BUCK3_ STAT	BUCK3_ PG_STAT	Reserved	BUCK3_ ILIM_STAT	BUCK2_ STAT	BUCK2_ PG_STAT	Reserved	BUCK2_ ILIM_STAT
0x21	TOP_ MASK1	R/W	Reserved	Reserved		SYNC_CLK _MASK	Reserved	TDIE_WARN_MASK	Reserved	I_LOAD_ READY_ MASK
0x22	TOP_ MASK2	R/W	Reserved							RESET_ REG_MASK
0x23	BUCK_0_1_MASK	R/W	Reserved	BUCK1_ PG_MASK	Reserved	BUCK1_ ILIM_ MASK	Reserved	BUCK0_ PG_MASK	Reserved	BUCK0_ ILIM_ MASK
0x24	BUCK_2_3_MASK	R/W	Reserved	BUCK3_ PG_MASK	Reserved	BUCK3_ ILIM_ MASK	Reserved	BUCK2_ PG_MASK	Reserved	BUCK2_ ILIM_ MASK
0x25	SEL_I_ LOAD	R/W	Reserved						LOAD_CURRENT_ BUCK_SELECT[1:0]
0x26	I_LOAD_2	R	Reserved						BUCK_LOAD_CURRENT[9:8]
0x27	I_LOAD_1	R	BUCK_LOAD_CURRENT[7:0]
0x28	PGOOD _CTRL1	R/W	PG3_SEL[1:0]		PG2_SEL[1:0]		PG1_SEL[1:0]		PG0_SEL[1:0]
0x29	PGOOD _CTRL2	R/W	HALF_DELAY	EN_PG0_ NINT	PGOOD_SET_ DELAY	EN_PGFLT _STAT	Reserved	PGOOD_WINDOW	PGOOD_OD	PGOOD_POL
0x2A	PGOOD_FLT	R					PG3_FLT	PG2_FLT	PG1_FLT	PG0_FLT
0x2B	PLL_CTRL	R/W	PLL_MODE[1:0]		Reserved	EXT_CLK_FREQ[4:0]
0x2C	PIN_ FUNCTION	R/W	EN_ SPREAD _SPEC	EN_PIN_CTRL _GPIO3	EN_PIN_SELECT _GPIO3	EN_PIN_CTRL _GPIO2	EN_PIN_SELECT _GPIO2	GPIO3_SEL	GPIO2_SEL	GPIO1_SEL
0x2D	GPIO_ CONFIG	R/W	Reserved	GPIO3_OD	GPIO2_OD	GPIO1_OD	Reserved	GPIO3_DIR	GPIO2_DIR	GPIO1_DIR
0x2E	GPIO_IN	R	Reserved					GPIO3_IN	GPIO2_IN	GPIO1_IN
0x2F	GPIO_OUT	R/W	Reserved					GPIO3_OUT	GPIO2_OUT	GPIO1_OUT