JAJSE47B April 2017 – December 2018 LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
Address: 0x29
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| HALF_DELAY | EN_PG0
_NINT |
PGOOD_SET
_DELAY |
EN_PGFLT
_STAT |
Reserved | PGOOD_
WINDOW |
PGOOD_OD | PGOOD_POL |
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7 | HALF_DELAY | R/W | 0 for LP87524B, LP87524J, 1 for LP87524P* | Select the time step for start-up and shutdown delays:
0 - Start-up and shutdown delays have 0.5-ms or 1-ms time steps, based on DOUBLE_DELAY bit in CONFIG register. 1 - Start-up and shutdown delays have 0.32-ms or 0.64-ms time steps, based on DOUBLE_DELAY bit in CONFIG register. |
| 6 | EN_PG0_NINT | R/W | 0 * | Combine Buck0 PGOOD signal to nINT signal:
0 - Buck0 PGOOD signal not included to nINT signal 1 - Buck0 PGOOD signal included to nINT signal. If nINT OR Buck0 PGOOD is low then nINT signal is low. |
| 5 | PGOOD_SET_DELAY | R/W | 1 * | Debounce time of output voltage monitoring for PGOOD signal (only when PGOOD signal goes valid):
0 - 4-10 µs 1 - 11 ms |
| 4 | EN_PGFLT_STAT | R/W | 0 * | Operation mode for PGOOD signal:
0 - Indicates live status of monitored voltage outputs. 1 - Indicates status of PGOOD_FLT register, inactive if at least one of PGx_FLT bit is inactive. |
| 3 | Reserved | R/W | 0 | |
| 2 | PGOOD_WINDOW | R/W | 1 * | Voltage monitoring method for PGOOD signal:
0 - Only undervoltage monitoring 1 - Overvoltage and undervoltage monitoring |
| 1 | PGOOD_OD | R/W | 1 * | PGOOD signal type:
0 - Push-pull output (VANA level) 1 - Open-drain output |
| 0 | PGOOD_POL | R/W | 0 * | PGOOD signal polarity:
0 - PGOOD signal high when monitored outputs are valid 1 - PGOOD signal low when monitored outputs are valid |