JAJSE47B April   2017  – December 2018 LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     概略回路図
  3. 3 概要
    1.     効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 概要（続き）
    1.     Device Images
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Descriptions
      1. 8.3.1 DC-DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Transition Between PWM and PFM Modes
        3. 8.3.1.3 Buck Converter Load-Current Measurement
        4. 8.3.1.4 Spread-Spectrum Mode
      2. 8.3.2 Sync Clock Functionality
      3. 8.3.3 Power-Up
      4. 8.3.4 Regulator Control
        1. 8.3.4.1 Enabling and Disabling Regulators
        2. 8.3.4.2 Changing Output Voltage
      5. 8.3.5 Enable and Disable Sequences
      6. 8.3.6 Device Reset Scenarios
      7. 8.3.7 Diagnosis and Protection Features
        1. 8.3.7.1 Power-Good Information (PGOOD pin)
        2. 8.3.7.2 Warnings for Diagnosis (Interrupt)
          1. 8.3.7.2.1 Output Power Limit
          2. 8.3.7.2.2 Thermal Warning
        3. 8.3.7.3 Protection (Regulator Disable)
          1. 8.3.7.3.1 Short-Circuit and Overload Protection
          2. 8.3.7.3.2 Overvoltage Protection
          3. 8.3.7.3.3 Thermal Shutdown
        4. 8.3.7.4 Fault (Power Down)
          1. 8.3.7.4.1 Undervoltage Lockout
      8. 8.3.8 GPIO Signal Operation
      9. 8.3.9 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto-Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1  OTP_REV
        2. 8.6.1.2  BUCK0_CTRL1
        3. 8.6.1.3  BUCK1_CTRL1
        4. 8.6.1.4  BUCK2_CTRL1
        5. 8.6.1.5  BUCK3_CTRL1
        6. 8.6.1.6  BUCK0_VOUT
        7. 8.6.1.7  BUCK0_FLOOR_VOUT
        8. 8.6.1.8  BUCK1_VOUT
        9. 8.6.1.9  BUCK1_FLOOR_VOUT
        10. 8.6.1.10 BUCK2_VOUT
        11. 8.6.1.11 BUCK2_FLOOR_VOUT
        12. 8.6.1.12 BUCK3_VOUT
        13. 8.6.1.13 BUCK3_FLOOR_VOUT
        14. 8.6.1.14 BUCK0_DELAY
        15. 8.6.1.15 BUCK1_DELAY
        16. 8.6.1.16 BUCK2_DELAY
        17. 8.6.1.17 BUCK3_DELAY
        18. 8.6.1.18 GPIO2_DELAY
        19. 8.6.1.19 GPIO3_DELAY
        20. 8.6.1.20 RESET
        21. 8.6.1.21 CONFIG
        22. 8.6.1.22 INT_TOP1
        23. 8.6.1.23 INT_TOP2
        24. 8.6.1.24 INT_BUCK_0_1
        25. 8.6.1.25 INT_BUCK_2_3
        26. 8.6.1.26 TOP_STAT
        27. 8.6.1.27 BUCK_0_1_STAT
        28. 8.6.1.28 BUCK_2_3_STAT
        29. 8.6.1.29 TOP_MASK1
        30. 8.6.1.30 TOP_MASK2
        31. 8.6.1.31 BUCK_0_1_MASK
        32. 8.6.1.32 BUCK_2_3_MASK
        33. 8.6.1.33 SEL_I_LOAD
        34. 8.6.1.34 I_LOAD_2
        35. 8.6.1.35 I_LOAD_1
        36. 8.6.1.36 PGOOD_CTRL1
        37. 8.6.1.37 PGOOD_CTRL2
        38. 8.6.1.38 PGOOD_FLT
        39. 8.6.1.39 PLL_CTRL
        40. 8.6.1.40 PIN_FUNCTION
        41. 8.6.1.41 GPIO_CONFIG
        42. 8.6.1.42 GPIO_IN
        43. 8.6.1.43 GPIO_OUT
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Inductor Selection
        2. 9.2.1.2 Input Capacitor Selection
        3. 9.2.1.3 Output Capacitor Selection
        4. 9.2.1.4 Snubber Components
        5. 9.2.1.5 Supply Filtering Components
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RNF|26
サーマルパッド・メカニカル・データ
発注情報

8.3.5 Enable and Disable Sequences

The LP87524B/J/P-Q1 device supports start-up and shutdown sequencing with programmable delays for different regulator outputs using single EN1/2/3 control signal. The regulator is selected for delayed control with:

  • EN_BUCKx = 1 (in BUCKx_CTRL1 register)
  • EN_PIN_CTRLx = 1 (in BUCKx_CTRL1 register)
  • EN_ROOF_FLOORx = 0 (in BUCKx_CTRL1 register)
  • BUCKx_VSET[7:0] = Required voltage when ENx is high (in BUCKx_VOUT register)
  • The ENABLE pin for control is selected with BUCKx_EN_PIN_SELECT[1:0] (in BUCKx_CTRL1 register)
  • The delay from rising edge of ENx signal to the regulator enable is set by BUCKx_STARTUP_DELAY[3:0] bits (in BUCKx_DELAY register) and
  • The delay from falling edge of ENx signal to the regulator disable is set by BUCKx_SHUTDOWN_DELAY[3:0] bits (in BUCKx_DELAY register)

There are four time steps available for start-up and shutdown sequences. The delay times are selected with DOUBLE_DELAY bit in CONFIG register and HALF_DELAY bit in PGOOD_CTRL2 register as shown in Table 4.

Table 4. Start-up and Shutdown Delays

X_STARTUP_DELAY /
X_SHUTDOWN_DELAY		 DOUBLE_DELAY = 0
HALF_DELAY = 1		 DOUBLE_DELAY = 1
HALF_DELAY = 1		 DOUBLE_DELAY = 0
HALF_DELAY = 0		 DOUBLE_DELAY = 1
HALF_DELAY = 0
0000 0 ms 0 ms 0 ms 0 ms
0001 0.32 ms 0.64 ms 1 ms 2 ms
0010 0.64 ms 1.28 ms 2 ms 4 ms
0011 0.96 ms 1.92 ms 3 ms 6 ms
0100 1.28 ms 2.56 ms 4 ms 8 ms
0101 1.6 ms 3.2 ms 5 ms 10 ms
0110 1.92 ms 3.84 ms 6 ms 12 ms
0111 2.24 ms 4.48 ms 7 ms 14 ms
1000 2.56 ms 5.12 ms 8 ms 16 ms
1001 2.88 ms 5.76 ms 9 ms 18 ms
1010 3.2 ms 6.4 ms 10 ms 20 ms
1011 3.52 ms 7.04 ms 11 ms 22 ms
1100 3.84 ms 7.68 ms 12 ms 24 ms
1101 4.16 ms 8.32 ms 13 ms 26 ms
1110 4.48 ms 8.96 ms 14 ms 28 ms
1111 4.8 ms 9.6 ms 15 ms 30 ms

An example of start-up and shutdown sequences is shown in Figure 10 and Figure 11. The start-up and shutdown delays for the Buck0/1 regulators are 1 ms and 4 ms and for the Buck2/3 regulators 3 ms and 1 ms. The delay settings are used only for enable/disable control with EN1/2/3 signals, not for Roof/Floor control.

LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 Sequencing.gifFigure 10. Typical Start-Up and Shutdown Sequencing
LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 Sequencing_2.gifFigure 11. Start-Up and Shutdown Sequencing With Short ENx Low and High Periods