JAJSE47B April 2017 – December 2018 LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1
PRODUCTION DATA.
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Address: 0x18
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
Reserved | SW_RESET |
Bits | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | Reserved | R/W | 0x00 | |
0 | SW_RESET | R/W | 0 | Software commanded reset. When written to 1, the registers are reset to default values, OTP memory is read, and the I2C interface is reset.
The bit is automatically cleared. |