JAJSO71 March   2022 LP8764-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 説明
  4. Revision History
  5. Pin Configuration and Functions
    1. 5.1 Digital Signal Descriptions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Internal Low Drop-Out Regulators (LDOVINT)
    6. 6.6  BUCK1, BUCK2, BUCK3, and BUCK4 Regulators
    7. 6.7  Reference Generator (REFOUT)
    8. 6.8  Monitoring Functions
    9. 6.9  Clocks, Oscillators, and DPLL
    10. 6.10 Thermal Monitoring and Shutdown
    11. 6.11 System Control Thresholds
    12. 6.12 Current Consumption
    13. 6.13 Digital Input Signal Parameters
    14. 6.14 Digital Output Signal Parameters
    15. 6.15 I/O Pullup and Pulldown Resistance
    16. 6.16 I2C Interface
    17. 6.17 Serial Peripheral Interface (SPI)
      1.      25
  7. Typical Characteristics
  8. Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Input Voltage Monitor
    4. 8.4  Device State Machine
      1. 8.4.1 Fixed Device Power FSM
        1. 8.4.1.1 Register Resets and EEPROM read at INIT state
      2. 8.4.2 Pre-Configurable Mission States
        1. 8.4.2.1 PFSM Commands
          1. 8.4.2.1.1  REG_WRITE_IMM Command
          2. 8.4.2.1.2  REG_WRITE_MASK_IMM Command
          3. 8.4.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
          4. 8.4.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
          5. 8.4.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
          6. 8.4.2.1.6  REG_WRITE_VOUT_IMM Command
          7. 8.4.2.1.7  REG_WRITE_VCTRL_IMM Command
          8. 8.4.2.1.8  REG_WRITE_MASK_SREG Command
          9. 8.4.2.1.9  SREG_READ_REG Command
          10. 8.4.2.1.10 SREG_WRITE_IMM Command
          11. 8.4.2.1.11 WAIT Command
          12. 8.4.2.1.12 DELAY_IMM Command
          13. 8.4.2.1.13 DELAY_SREG Command
          14. 8.4.2.1.14 TRIG_SET Command
          15. 8.4.2.1.15 TRIG_MASK Command
          16. 8.4.2.1.16 END Command
        2. 8.4.2.2 Configuration Memory Organization and Sequence Execution
        3. 8.4.2.3 Mission State Configuration
        4. 8.4.2.4 Pre-Configured Hardware Transitions
          1. 8.4.2.4.1 ON Requests
          2. 8.4.2.4.2 OFF Requests
            1. 8.4.2.4.2.1 NSLEEP1 and NSLEEP2 Functions
            2. 8.4.2.4.2.2 WKUP1 and WKUP2 Functions
      3. 8.4.3 Error Handling Operations
        1. 8.4.3.1 Power Rail Output Error
        2. 8.4.3.2 Boot BIST Error
        3. 8.4.3.3 Runtime BIST Error
        4. 8.4.3.4 Catastrophic Error
        5. 8.4.3.5 Watchdog (WDOG) Error
        6. 8.4.3.6 Error Signal Monitor (ESM) Error
        7. 8.4.3.7 Warnings
      4. 8.4.4 Device Start-up Timing
      5. 8.4.5 Power Sequences
      6. 8.4.6 First Supply Detection
    5. 8.5  Power Resources
      1. 8.5.1 Buck Regulators
        1. 8.5.1.1 BUCK Regulator Overview
        2. 8.5.1.2 Multi-Phase Operation and Phase-Adding or Shedding
        3. 8.5.1.3 Transition Between PWM and PFM Modes
        4. 8.5.1.4 Spread-Spectrum Mode
        5. 8.5.1.5 Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
        6. 8.5.1.6 BUCK Output Voltage Setting
      2. 8.5.2 Sync Clock Functionality
      3. 8.5.3 Internal Low Dropout Regulator (LDOVINT)
    6. 8.6  Residual Voltage Checking
    7. 8.7  Output Voltage Monitor and PGOOD Generation
    8. 8.8  General-Purpose I/Os (GPIO Pins)
    9. 8.9  Thermal Monitoring
      1. 8.9.1 Thermal Warning Function
      2. 8.9.2 Thermal Shutdown
    10. 8.10 Interrupts
    11. 8.11 Control Interfaces
      1. 8.11.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 8.11.2 I2C-Compatible Interface
        1. 8.11.2.1 Data Validity
        2. 8.11.2.2 Start and Stop Conditions
        3. 8.11.2.3 Transferring Data
        4. 8.11.2.4 Auto-Increment Feature
      3. 8.11.3 Serial Peripheral Interface (SPI)
    12. 8.12 Multi-PMIC Synchronization
      1. 8.12.1 SPMI Interface System Setup
      2. 8.12.2 Transmission Protocol and CRC
        1. 8.12.2.1 Operation with Transmission Errors
        2. 8.12.2.2 Transmitted Information
      3. 8.12.3 SPMI Target Device Communication to SPMI Controller Device
        1. 8.12.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
      4. 8.12.4 SPMI-BIST Overview
        1. 8.12.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
        2. 8.12.4.2 Periodic Checking of the SPMI
        3. 8.12.4.3 SPMI Message Priorities
    13. 8.13 NVM Configurable Registers
      1. 8.13.1 Register Page Partitioning
      2. 8.13.2 CRC Protection for Configuration, Control, and Test Registers
      3. 8.13.3 CRC Protection for User Registers
      4. 8.13.4 Register Write Protection
        1. 8.13.4.1 ESM and WDOG Configuration Registers
        2. 8.13.4.2 User Registers
    14. 8.14 Watchdog (WD)
      1. 8.14.1 Watchdog Fail Counter and Status
      2. 8.14.2 Watchdog Start-Up and Configuration
      3. 8.14.3 MCU to Watchdog Synchronization
      4. 8.14.4 Watchdog Disable Function
      5. 8.14.5 Watchdog Sequence
      6. 8.14.6 Watchdog Trigger Mode
      7. 8.14.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
      8.      121
      9. 8.14.8 Watchdog Question-Answer Mode
        1. 8.14.8.1 Watchdog Q&A Related Definitions
        2. 8.14.8.2 Question Generation
        3. 8.14.8.3 Answer Comparison
          1. 8.14.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
          2. 8.14.8.3.2 Watchdog Sequence Events and Status Updates
          3. 8.14.8.3.3 Watchdog Q&A Sequence Scenarios
    15. 8.15 Error Signal Monitor (ESM)
      1. 8.15.1 ESM Error-Handling Procedure
      2. 8.15.2 Level Mode
      3.      132
      4. 8.15.3 PWM Mode
        1. 8.15.3.1 Good-Events and Bad-Events
        2. 8.15.3.2 ESM Error-Counter
          1. 8.15.3.2.1 ESM Start-Up in PWM Mode
        3. 8.15.3.3 ESM Flow Chart and Timing Diagrams in PWM Mode
        4.       138
    16. 8.16 Register Map
      1. 8.16.1 LP8764x_map Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Buck Inductor Selection
        2. 9.2.1.2 Buck Input Capacitor Selection
        3. 9.2.1.3 Buck Output Capacitor Selection
        4. 9.2.1.4 LDO Output Capacitor Selection
        5. 9.2.1.5 VCCA Supply Filtering Components
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Voltage Scaling Precautions
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

BUCK1, BUCK2, BUCK3, and BUCK4 Regulators

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics - Output Voltage
3.1a VVOUT_Bx_Step Output voltage programmable step size 0.3 V ≤ VVOUT_Bx < 0.6 V 20 mV
3.1b 0.6 V ≤ VVOUT_Bx < 1.1 V 5
3.1c 1.1 V ≤ VVOUT_Bx < 1.66 V 10
3.1d 1.66 V ≤ VVOUT_Bx ≤ 3.34 V 20
3.3 Input and output voltage difference Minimum voltage between PVIN_Bx and VOUT_Bx to fulfill the electrical characteristics 0.7 V
3.4a VVOUT_Bx_Slew_Rate Output voltage slew-rate programmable range(5)(7)(9) BUCKn_SLEW_RATE[2:0] = 000b 26.6 33.3 36.6 mV/µs
3.4b BUCKn_SLEW_RATE[2:0] = 001b 17 20 22
3.4c BUCKn_SLEW_RATE[2:0] = 010b 9 10 11
3.4d BUCKn_SLEW_RATE[2:0] = 011b 4.5 5 5.5
3.4e BUCKn_SLEW_RATE[2:0] = 100b 2.25 2.5 2.75
3.4f BUCKn_SLEW_RATE[2:0] = 101b 1.12 1.25 1.38
3.4g BUCKn_SLEW_RATE[2:0] = 110b 0.56 0.625 0.69
3.4h BUCKn_SLEW_RATE[2:0] = 111b 0.281 0.3125 0.344
Electrical Characteristics - Output Current, Limits and Thresholds
3.6a IOUT_Bx Output current(3)(4) 1-phase 5 A
3.6b 2-phase 10
3.6c 3-phase 15
3.6d 4-phase 20
3.7 Current balancing for multi-phase output Mismatch between phase current and average phase current, IOUT_Bx > 1 A / phase 20%
3.8 ILIM FWD PEAK Range Forward current limit (peak during each switching cycle) Programmable range 2.5 7.5  A
3.9 ILIM FWD PEAK Step Forward current limit step Size 1 A
3.10a ILIM FWD PEAK Accuracy Forward current limit accuracy ILIM = 2.5 A, 3.5 A, 4.5 A, 3.0 V ≤ VPVIN_Bx ≤ 5.5 V -0.55 0.55 A
3.10b ILIM = 5.5 A, 6.5 A or 7.5 A 4.5 V ≤ VPVIN_Bx ≤ 5.5 V –10% 10%
3.10c ILIM = 5.5 A, 6.5 A or 7.5 A 3.0 V ≤ VPVIN_Bx ≤ 4.5 V –15% 10%
3.11 ILIM NEG Negative current limit (peak during each switching cycle) 1.5 2 2.6 A
3.15a IADD Phase adding level (multi-phase rails) From 1-phase to 2-phase 2.0 A
3.15b From 2-phase to 3-phase 3.6
3.15c From 3-phase to 4-phase 5.5
3.16a ISHED Phase shedding level (multi-phase rails) From 2-phase to 1-phase 1.4 A
3.16b From 3-phase to 2-phase 2.5
3.16c From 4-phase to 3-phase 3.3
3.16d ISHED_Hyst Phase shedding hysteresis (multi-phase rails) Hysteresis from 2-phase to 1-phase 0.6 A
3.16e Hysteresis from 3-phase to 2-phase 1.4
3.16f Hysteresis from 4-phase to 3-phase 2.5
Electrical Characteristics - Current Consumption, On Resistance, and Output Pulldown Resistance
3.17 Ioff Shutdown current, BUCKx disabled 1 µA
3.18a IQ_AUTO Auto mode quiescent current IOUT_Bn = 0 mA, not switching, first single
phase or primary phase in multi-phase
configuration, TJ = 25°C
90 µA
3.18b IOUT_Bn = 0 mA, not switching, additional
single phase or primary phase in multi-phase
configuration, TJ = 25°C
60
3.18c IOUT_Bn = 0 mA, not switching, secondary/
tertiary/quaternary phase in multi-phase
configuration, TJ = 25°C
30
3.19 RDS(ON) HS FET On-resistance, high-side FET IOUT_Bx = 1 A 26 65
3.20 RDS(ON) LS FET On-resistance, low-side FET IOUT_Bx = 1 A 16 35
3.21 RDIS_Bx Output pulldown discharge resistance Regulator disabled, per phase, BUCKx_PLDN = 1, between SW_Bx and PGND pins 50 100 150 Ω
3.21b VTH_SC_RV_Bx Threshold voltage for Short Circuit and Residual Voltage Detection 140 150 160 mV
3.22 RSW_SC Resistance threshold for Short circuit detection at the SW pin 3 5 25 Ω
Electrical Characteristics - 4.4MHz Single-Phase and Multi-Phase Configuration
3.23 VPVIN_Bx Input voltage range 3.0 3.3 5.5 V
3.24 VVOUT_Bx Output voltage programmable range 0.3 1.9 V
3.25 CIN_Bx Input filtering capacitance(1)(2) 3 22 µF
3.26a COUT-Local(Buckx) Output capacitance, local(2) Per phase 10 22 µF
3.27b COUT-TOTAL_Bx Output capacitance, total (local and POL)(2) Per phase 50 250 µF
3.28a LBx Power inductor Inductance 154 220 286 nH
3.28b DCR 10
3.29 IQ_PWM PWM mode Quiescent current IOUT_Bx = 0 mA 20 mA
3.160a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV
3.160b VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
3.160c VVOUT_Bx < 1 V, PFM mode –20 25 mV
3.160d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV
3.31a TLDSR_MP Transient load step response(8) 0.3 V ≤ VVOUT_Bx < 0.6 V, IOUT_Bx = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 15 mV
3.31b 0.6 V ≤ VVOUT_Bx < 1.5 V, IOUT_Bx = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode 15 mV
3.31c 1.5 V ≤ VVOUT_Bx ≤ 1.9 V, IOUT_Bx = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode  1.5%
3.32 TLNSR Transient line response VPVIN_Bx stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bx = IOUT(max) -20 ±5 20 mV
3.33a VOUT_Ripple Ripple voltage(8) PWM mode, 1-phase 3 mVPP
3.33b PFM mode 15 25 mVPP
3.120 IPFM-PWM PFM to PWM switch current threshold(6) Auto mode 600 mA
3.121 IPWM-PFM PWM to PFM switch current threshold(6) Auto mode 300 mA
3.122 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode 200 mA
Electrical Characteristics - 2.2MHz Single-Phase Configuration for DDR Termination
3.34 VPVIN_Bx Input voltage range 2.8 3.3 5.5 V
3.35 IOUT_Bx_SINK Current sink 1 A
3.36 VVOUT_Bx Output voltage programmable range 0.5 0.7 V
3.37 CIN_Bx Input filtering capacitance(1)(2) 3 22 µF
3.38a COUT-Local(Buckx) Output capacitance, local(2) 10 22 µF
3.38b COUT-TOTAL_Bx Output capacitance, total (local and POL)(2) 25 50 µF
3.39a LBx Power inductor Inductance 329 470 611 nH
3.39b DCR 10
3.40 IQ_PWM PWM mode Quiescent current IOUT_Bx = 0 mA 13 mA
3.161a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV
3.161b VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
3.42 TLDSR Transient load step response(8) 0.5 V ≤ VVOUT_Bx ≤ 0.7 V, IOUT_Bx = -1 mA to -1000 mA, tr = tf = 1 µs, PWM mode 15 mV
3.43 TLNSR Transient line response VPVIN_Bx stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bx = IOUT_Bx(max) -20 ±5 20 mV
3.44 VOUT_Ripple Ripple voltage(8) PWM mode 3 6 mVPP
Electrical Characteristics - 4.4MHz Single-Phase Configuration Low Output Voltage
3.45 VPVIN_Bx Input voltage range 3.0 3.3 5.5 V
3.46 VVOUT_Bx Output voltage programmable range 0.3 1.9 V
3.47 CIN_Bx Input filtering capacitance(1)(2) 3 22 µF
3.48a COUT-Local(Buckx) Output capacitance, local(2) 10 22 µF
3.48b COUT-TOTAL_Bx Output capacitance, total (local and POL)(2) 25 100 µF
3.49a LBx Power inductor Inductance 154 220 286 nH
3.49b DCR 10
3.50 IQ_PWM PWM mode Quiescent current IOUT_Bx = 0 mA 19 mA
3.162a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV
3.162b VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
3.162c VVOUT_Bx < 1 V, PFM mode –20 35 mV
3.162d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 25 mV
3.52a TLDSR Transient load step response(8) 0.3 V ≤ VVOUT_Bx < 0.6 V, IOUT_Bx = 1 mA to 200 mA, tr = tf = 1 µs, PWM mode 15 mV
3.52b 0.6 V ≤ VVOUT_Bx < 1.5 V, IOUT_Bx = 1 mA to 1 A, tr = tf = 1 µs, PWM mode 15 mV
3.52c 1.5 V ≤ VVOUT_Bx ≤ 1.9 V, IOUT_Bx = 1 mA to 1 A, tr = tf = 1 µs, PWM mode 1.5%
3.53 TLNSR Transient line response VPVIN_Bxx stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bx= IOUT_Bx(max) -20 ±5 20 mV
3.54a VOUT_Ripple Ripple voltage(8) PWM mode 5 8 mVPP
3.54b PFM mode 15 50 mVPP
3.123 IPFM-PWM PFM to PWM switch current threshold(6) Auto mode, VPVIN_Bx = 3.3 V, VVOUT_Bx = 1.0 V 600 mA
3.124 IPWM-PFM PWM to PFM switch current threshold(6) Auto mode, VPVIN_Bx = 3.3 V, VVOUT_Bx = 1.0 V 300 mA
3.125 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bx = 3.3 V, VVOUT_Bx = 1.0 V 200 mA
Electrical Characteristics - 4.4MHz Single-Phase Configuration High Output Voltage
3.55 VPVIN_Bx Input voltage range 4.5 5 5.5 V
3.56 IOUT_Bx_4.4_HVOUT Output current 2.5 A
3.57 VVOUT_Bx Output voltage programmable range 1.7 3.34 V
3.58 CIN_Bx Input filtering capacitance(1)(2) 3 22 µF
3.59a COUT-Local_Bx Output capacitance, local(2) 10 22 µF
3.59b COUT-TOTAL_Bx Output capacitance, total (local and POL)(2) 50 150 µF
3.60a LBx Power inductor Inductance 329 470 611 nH
3.60b DCR 10
3.61 IQ_PWM PWM mode Quiescent current IOUT_Bx = 0 mA 29 mA
3.163a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV
3.163b VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
3.163c VVOUT_Bx < 1 V, PFM mode –20 25 mV
3.163d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV
3.63 TLDSR_SP Transient load step response(8) 1.7 V ≤ VVOUT_Bx ≤ 3.34 V, IOUT_Bx = 1 mA to 1 A, tr = tf = 1 µs, PWM mode 1.5%
3.64 TLNSR Transient line response VPVIN_Bxx stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bx = IOUT_Bx(max) -20 ±5 20 mV
3.65a VOUT_Ripple Ripple voltage(8) PWM mode 3 7 mVPP
3.65b PFM mode 15 25 mVPP
3.126 IPFM-PWM PFM to PWM switch current threshold(6) Auto mode, VPVIN_Bx = 5 V, VVOUT_Bx = 1.8 V 400 mA
3.127 IPWM-PFM PWM to PFM switch current threshold(6) Auto mode, VPVIN_Bx = 5 V, VVOUT_Bx = 1.8 V 260 mA
3.128 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bx = 5 V, VVOUT_Bx = 1.8 V 140 mA
Electrical Characteristics - 2.2MHz Single-Phase Configuration with 5.0V VIN
3.66 VPVIN_Bx Input voltage range 4.5 5 5.5 V
3.67 VVOUT_Bx Output voltage programmable range 0.3 3.34 V
3.68 CIN_Bx Input filtering capacitance(1)(2) 3 22 µF
3.69a COUT-Local_Bx Output capacitance, local(2) 10 22 µF
3.69b COUT-TOTAL_Bx Output capacitance, total (local and POL)(2) 100 1000 µF
3.70a LBx Power inductor Inductance 700 1000 1300 nH
3.70b DCR 10
3.71 IQ_PWM PWM mode Quiescent current IOUT_Bx = 0 mA 14 mA
3.164a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV
3.164b VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
3.164c VVOUT_Bx < 1 V, PFM mode –20 25 mV
3.164d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV
3.73a TLDSR_SP Transient load step response(8) 0.3 V ≤ VVOUT_Bx < 0.6 V, IOUT_Bx = 1 mA to 400 mA, tr = tf = 1 µs, PWM mode 15 mV
3.73b 0.6 V ≤ VVOUT_Bx < 1.5 V, IOUT_Bx = 1 mA to 2 A, tr = tf = 1 µs, PWM mode 15 mV
3.73c 1.5 V ≤ VVOUT_Bx ≤ 3.34 V, IOUT_Bx = 1 mA to 2 A, tr = tf = 1 µs, PWM mode 1.5%
3.74 TLNSR Transient line response VPVIN_Bx stepping from 4.7 V to 5.2 V, tr = tf = 10 µs, IOUT_Bx= IOUT_Bx(max) -20 ±5 20 mV
3.75a VOUT_Ripple Ripple voltage(8) PWM mode 3 7.5 mVPP
3.75b PFM mode 15 25 mVPP
3.129 IPFM-PWM PFM to PWM switch current threshold(6) Auto mode, VPVIN_Bx = 5 V, VVOUT_Bx = 1.0V 400 mA
3.130 IPWM-PFM PWM to PFM switch current threshold(6) Auto mode, VPVIN_Bx = 5 V, VVOUT_Bx = 1.0V 200 mA
3.131 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bx = 5 V, VVOUT_Bx = 1.0V 200 mA
Electrical Characteristics - 2.2MHz Single-Phase and Multi-Phase Configuration
3.76 VPVIN_Bx Input voltage range 3.0 3.3 5.5 V
3.77 VVOUT_Bx Output voltage programmable range 0.3 1.9 V
3.78 CIN_Bx Input filtering capacitance(1)(2) 3 22 µF
3.79a COUT-Local_Bx Output capacitance, local(2) Per phase 10 22 µF
3.79b COUT-TOTAL_Bx Output capacitance, total (local and POL)(2) Per phase 100 1000 µF
3.80a LBx Power inductor Inductance 329 470 611 nH
3.80b DCR 10
3.81 IQ_PWM PWM mode Quiescent current IOUT_Bx = 0 mA 13 mA
3.165a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV
3.165b VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
3.165c VVOUT_Bx < 1 V, PFM mode –20 25 mV
3.165d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV
3.83a TLDSR_MP Transient load step response(8) 0.3 V ≤ VVOUT_Bx < 0.6 V, IOUT_Bx = 1 mA to 400 mA / phase, tr = tf = 1 µs, PWM mode 5 mV
3.83b 0.6 V ≤ VVOUT_Bx < 1.5 V, IOUT_Bx = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode  15 mV
3.83c 1.5 V ≤ VVOUT_Bx ≤ 1.9 V, IOUT_Bx = 1 mA to 2 A / phase, tr = tf = 1 µs, PWM mode  1%
3.84 TLNSR Transient line response VPVIN_Bx stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bx = IOUT_Bx(max) -20 ±5 20 mV
3.85a VOUT_Ripple Ripple voltage(8) PWM mode, 1-phase 3 5 mVPP
3.85b PFM mode 15 25 mVPP
3.132 IPFM-PWM PFM to PWM switch current threshold(6) Auto mode, VPVIN_Bx = 3.3 V, VVOUT_Bx = 1.0V 500 mA
3.133 IPWM-PFM PWM to PFM switch current threshold(6) Auto mode, VPVIN_Bx = 3.3 V, VVOUT_Bx = 1.0V 440 mA
3.134 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bx = 3.3 V, VVOUT_Bx = 1.0V 60 mA
Electrical Characteristics - 2.2MHz Single-Phase Generic Configuration
3.86 VPVIN_Bx Input voltage range 2.8 3.3 5.5 V
3.87 VVOUT_Bx Output voltage programmable range 0.3 3.34 V
3.88 CIN_Bx Input filtering capacitance(1)(2) 3 22 µF
3.89a COUT-Local_Bx Output capacitance, local(2) 10 22 µF
3.89b COUT-TOTAL_Bx Output capacitance, total (local and POL)(2) 100 500 µF
3.90a LBx Power inductor Inductance 700 1000 1300 nH
3.90b DCR 10
3.91 IQ_PWM PWM mode Quiescent current IOUT_Bx = 0 mA 13 mA
3.166a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV
3.166b VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
3.166c VVOUT_Bx < 1 V, PFM mode –20 25 mV
3.166d VVOUT_Bx ≥ 1 V, PFM mode -1% - 10 mV 1% + 15 mV
3.93a TLDSR_SP Transient load step response(8) 0.3 V ≤ VVOUT_Bx < 0.6 V, IOUT_Bx = 1 mA to 400 mA, tr = tf = 1 µs, PWM mode 35 mV
3.93b 0.6 V ≤ VVOUT_Bx < 1.0 V, IOUT_Bx = 1 mA to 2 A, tr = tf = 1 µs, PWM mode 17 mV
3.93c 1.0 V ≤ VVOUT_Bx ≤ 3.34 V, IOUT_Bx = 1 mA to 2 A, tr = tf = 1 µs, PWM mode 3.5%
3.94 TLNSR Transient line response VPVIN_Bx stepping from 3 V to 3.5 V, tr = tf = 10 µs, IOUT_Bx = IOUT_Bx(max) -20 ±5 20 mV
3.95a VOUT_Ripple Ripple voltage(8) PWM mode 3 7.5 mVPP
3.95b PFM mode 15 25 mVPP
3.135 IPFM-PWM PFM to PWM switch current threshold(6) Auto mode, VPVIN_Bx = 3.3 V, VVOUT_Bx = 1.0V 300 mA
3.136 IPWM-PFM PWM to PFM switch current threshold(6) Auto mode, VPVIN_Bx = 3.3 V, VVOUT_Bx = 1.0V 150 mA
3.137 IPWM-PFM_HYST PWM to PFM switch current hysteresis Auto mode, VPVIN_Bx = 3.3 V, VVOUT_Bx = 1.0V 150 mA
Timing Requirements
3.108 Settling time after voltage scaling From end of voltage ramp to VOUT within 15 mV from VOUT_DC_Bx(10) 105 µs
3.109 Start-up delay From enable to start of output voltage rise 100 150 200 µs
3.110 tdelay_OC Over-current detection delay Peak current limit triggering during every switching cycle 7 µs
3.111 tdeglitch_OC Over-current detection signal deglitch time Digital deglitch time for detected signal. Time duration to filter out short positive and negative pulses 19 23 µs
3.112 tlatency_OC Over-current signal latency time from detection Total delay from over-current detection to interrupt or PFSM trigger 30 µs
Switching Characteristics
3.106a fSW Switching frequency, PWM mode NVM programmable 2.2 MHz setting, internal clock 2 2.2 2.4 MHz
3.106b 4.4 MHz setting, internal clock 4 4.4 4.8
3.106d 2.2 MHz setting, internal clock, spread spectrum enabled 1.8 2.2 2.6
3.106e 4.4 MHz setting, internal clock, spread spectrum enabled 3.5 4.4 5.3
3.106g 2.2 MHz setting, synchronized to external clock 1.8 2.2 2.6
3.106h 4.4 MHz setting, synchronized to external clock 3.5 4.4 5.3
3.107b fSW_max Automatic maximum switching frequency scaling in PWM mode 0.3 V ≤ VVOUT_Bx < 0.6 V 2.2 MHz
Input capacitors must be placed as close as possible to the device pins.
When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of regulators.
The maximum output current can be limited by the forward current limit ILIM FWD. The maximum output current is also limited by the junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature.
Advance thermal design is required to avoid thermal shutdown.
SLEW_RATEx[2:0] register default comes from NVM memory, and can be re-programed by software. Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates.
The PFM-to-PWM and PWM-to-PFM switchover current can be affected by the input and  the output voltage, temperature, the inductor and the capacitor values.
A high slew-rate setting can generate over and undershoot during voltage change. See Application Section for more information.
Please refer to the applications section of the datasheet regarding the power delivery network (PDN) used for the transient load step and output ripple test conditions. All ripple specs are defined across POL capacitor in the described PDN.
Slew-rate is measured from 10% to 90% of the voltage ramp with voltage step ≥ 500 mV.
Voltage ramp is calculated using slew-rate from minimum column.