JAJSOM4 December 2023 LP87725-Q1
PRODUCTION DATA
| PIN NAME | POWER DOMAIN (recommended max) | INTERNAL PU/PD | DEGLITCH TIME |
|---|---|---|---|
| nERR | VCCA | 10 kΩ PU to VCCA | 15 µs |
| WD_DIS | VCCA | - | 30 µs |
| SCL | VCCA | - | - |
| SDA | VCCA | - | - |
| VMON1 | VCCA | - | LDO_LS1_VMON1_DEGLITCH_SEL |
| VMON2 | VCCA | - | LS2_VMON2_DEGLITCH_SEL |
| SYNCCLK | VCCA | 400 kΩ PD to GND | - |
| ENABLE | VCCA | 400 kΩ PD to GND | 8 µs |
| GPIO ( I2C Address select) | VCCA | - | 8 µs |
ENABLE input is always functional when VCCA is at the valid level. Other input buffers are disabled until the valid VCCA supply is present and the device startup has progressed to a certain state. The input buffers are enabled after the OTP is read.
| PIN NAME | POWER DOMAIN | PIN MODE | OUTPUT TYPE | INTERNAL PU/PD |
|---|---|---|---|---|
| SDA | VCCA | - | - | |
| nRSTOUT | VCCA | - | Open-drain or push-pull Active low or active high | In OD mode 10 kΩ programmable PU to VCCA when output driven high. PU disabled when output driven low. |
| nINT/GPO | VCCA | - | Open-drain or push-pull Active low or active high | In OD mode 10 kΩ programmable PU to VCCA when output driven high. PU disabled when output driven low. |