JAJSFL7B June   2018  – April 2021 LSF0204-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.8 V)
    7. 6.7  Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.2 V)
    8. 6.8  Switching Characteristics: AC Performance (Translating Up, 1.8 V to 3.3 V)
    9. 6.9  Switching Characteristics: AC Performance (Translating Up, 1.2 V to 1.8 V)
    10. 6.10 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Auto-Bidirectional Voltage Translation Without DIR Pin Terminal
      2. 7.3.2 Support Multiple High Speed Translation Interfaces
      3. 7.3.3 5-V Tolerance on IO Port and 125°C Support
      4. 7.3.4 Channel Specific Translation
      5. 7.3.5 Ioff, Partial Power Down Mode
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 I2C, PMBus, SMBus, GPIO Application
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Bidirectional Translation
            1. 8.2.1.2.1.1 Pull-Up Resistor Sizing
        3. 8.2.1.3 Application Curve
      2. 8.2.2 MDIO Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Multiple Voltage Translation in Single Device, Application
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報
Pull-Up Resistor Sizing

The pull-up resistor value needs to limit the current through the pass transistor when it is in the ON state to about 15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than 15 mA, the pass voltage also is higher in the ON state. To set the current through each pass transistor at 15 mA, to calculate the pull-up resistor value use Equation 1.

Equation 1. Rpu = (Vpu – 0.35 V) / 0.015 A

Table 8-3 summarizes resistor values, reference voltages, and currents at 15 mA, 10 mA, and 3 mA. The resistor value shown in the +10% column (or a larger value) should be used to ensure that the pass voltage of the transistor is 350 mV or less. The external driver must be able to sink the total current from the resistors on both sides of the LSF0204-Q1 device at 0.175 V, although the 15 mA applies only to current flowing through the LSF0204-Q1 device.

The LSF0204-Q1 does not provide any drive capability. Therefore higher frequency applications will require higher drive strength from the host side. No pullup resistor is needed on the host side (3.3 V) if the LSF0204-Q1 is being driven by standard CMOS totem pole output driver. Best practice is to minimize the trace length from the LSF0204-Q1 on the sink side (1.8 V) to minimize signal degradation.

Table 8-3 Pull-Up Resistor Values
PULLUP RESISTOR VALUE (Ω)
VDPU15 mA10mA3 mA
NOMINAL+10%(1)NOMINAL+10%(1)NOMINAL+10%(1)
5 V31034146551215501705
3.3 V1972172953259831082
2.5 V143158215237717788
1.8 V97106145160483532
1.5 V7785115127383422
1.2 V57638594283312
+10% to compensate for VDD range and resistor tolerance.