JAJSQL6B July   2014  – September 2023 LV284

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed Frequency PWM Control
      2. 7.3.2 Bootstrap Voltage (CB)
      3. 7.3.3 Setting the Ouput Voltage
      4. 7.3.4 Enable (SHDN) and VIN Undervoltage Lockout
      5. 7.3.5 Current Limit
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Conduction Mode
      2. 7.4.2 Eco-mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 5 V Output Application
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Design Guide – Step By Step Design Procedure
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Output Inductor Selection
          2. 8.2.1.2.2 Output Capacitor Selection
          3. 8.2.1.2.3 Schottky Diode Selection
          4. 8.2.1.2.4 Input Capacitor Selection
          5. 8.2.1.2.5 Bootstrap Capacitor Selection
        3. 8.2.1.3 Application Performance Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration

GUID-39EACA50-6F49-49BB-B0B2-B61E26B307DC-low.gif Figure 5-1 DDC Package, 6-Pin TSOT-6L (Top View)
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
CB 1 I SW FET gate bias voltage. Connect Cboot cap between CB and SW.
GND 2 G Ground Connection.
FB 3 I Feedback Pin. Set feedback voltage divider ratio with VOUT = VFB (1+(R1/R2))
SHDN 4 I Enable and disable input pin(high voltage tolerant). Internal pull-up current source. Pull below 1.25 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors.
VIN 5 I Power input voltage pin. Input for internal supply and drain node input for internal high-side MOSFET.
SW 6 O Switch node. Connect to inductor, diode and Cboot cap.