JAJSPA0Q
April 1999 – August 2024
MAX3243
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics –– Auto Power Down
5.6
Electrical Characteristics –– Driver
5.7
Electrical Characteristics –– Receiver
5.8
Switching Characteristics –– Auto Power Down
5.9
Switching Characteristics –– Driver
5.10
Switching Characteristics –– Receiver
5.11
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Auto-Power-Down
7.3.2
Charge Pump
7.3.3
RS232 Driver
7.3.4
RS232 Receiver
7.3.5
ROUT2B Receiver
7.3.6
Invalid Input Detection
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
ドキュメントの更新通知を受け取る方法
9.2
サポート・リソース
9.3
Trademarks
9.4
静電気放電に関する注意事項
9.5
用語集
10
Revision History
11
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DW|28
MPDS175A
DB|28
MPDS510A
PW|28
MPDS364
サーマルパッド・メカニカル・データ
DW|28
QFND317C
発注情報
jajspa0q_oa
8.2.1
Design Requirements
V
CC
minimum is 3 V and maximum is 5.5V.
Maximum recommended bit rate is 250 kbit/s.