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MCF8315C-Q1 は、速度制御された 12 ~ 24V ブラシレス DC モーター (BLDC) または永久磁石同期モーター (PMSM) を、最大 4A のピーク電流で駆動するための、シングルチップでコード フリーのセンサレス FOC ソリューションを提供します。MCF8315C-Q1 は、絶対最大定格が 40V で、RDS(ON) が 240/250/265mΩ (ハイサイドとローサイド FET の合計) という低い値のハーフ ブリッジを 3 つ内蔵しています。MCF8315C-Q1 には、電圧調整可能な降圧レギュレータ (3.3V/5V、170mA) および LDO (3.3V、20mA) を含む電源管理回路が内蔵されており、外部回路に電源を供給できます。
FOC アルゴリズムの構成は、不揮発性 EEPROM に保存されるため、構成後はデバイスをスタンドアロンで動作させることが可能です。デバイスは、PWM 入力、アナログ電圧、可変周波数の方形波、I2C コマンドによって速度コマンドを受信します。MCF8315C-Q1 は、本デバイス自身、モーター、システムをフォルト イベントから保護するための多くの保護機能を内蔵しています。
MCF8315C-Q1 は、40 ピンの 7x5mm ウェッタブル フランク QFN (RGF)、32 ピンの 6x4mm ウェッタブル フランク QFN (RRY)、および 24 ピンの 7.8x6.4mm HTSSOP (PWP) の 3 つのパッケージで供給されます。
部品番号 | パッケージ | パッケージ サイズ (2) |
---|---|---|
MCF8315C1VQRGFRQ1 | VQFN (40) | 7.00mm x 5.00mm |
MCF8315C1VQRRYRQ1(3) | WQFN (32) | 6.00mm × 4.00mm |
MCF8315C1VQPWPRQ1(3) | HTSSOP (24) | 7.80mm x 6.40mm |
PIN | 40-pin package | 32-pin package | 24-pin package | TYPE(1) | DESCRIPTION |
---|---|---|---|---|---|
NAME | MCF8315C-Q1 | MCF8315C-Q1 | MCF8315C-Q1 | ||
AGND | 26 | 19 | 16 | GND | Device analog ground. Refer Layout Guidelines for connection recommendation. |
ALARM | 39 | 30 | - | O | Alarm signal:
push-pull output. Pulled logic high during fault condition, if
enabled. If ALARM pin is not used, leave it floating. |
AVDD | 27 | 20 | 17 | PWR O | 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 20 mA for external circuits. |
BRAKE | 35 | 28 | 24 | I | High → Brake the
motor Low → Normal motor operation If BRAKE pin is not used, connect to AGND directly. If BRAKE pin is used to brake the motor, use an (optional) external 10-kΩ pull-down resistor (to AGND) for better noise rejection. |
CP | 8 | 7 | 9 | PWR | Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the CP and VM pins. |
CPH | 7 | 6 | 8 | PWR | Charge pump switching node. Connect a X5R or X7R, 47-nF, ceramic capacitor between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device. |
CPL | 6 | 5 | 7 | PWR | |
DACOUT1 | 36 | 29 | - | O | DAC output DACOUT1 |
DACOUT2 | 37 | - | - | O | DAC output DACOUT2 |
DACOUT2/SOX | 38 | - | - | O | Multi-purpose pin: DAC output when configured as DACOUT2 CSA output when configured as SOX |
DGND | 2 | 1 | 3 | GND | Device digital ground. Refer Layout Guidelines for connection recommendation. |
DIR | 34 | 27 | - | I | Direction of motor
spinning; When low, phase driving sequence is OUT A → OUT C → OUT B When high, phase driving sequence is OUT A → OUT B → OUT C If DIR pin is not used, connect to AGND or AVDD directly (depending on phase driving sequence needed). If DIR pin is used for changing motor spin direction, use an (optional) external 10-kΩ pulldown resistor (to AGND) for better noise rejection. |
DRVOFF | 21 | 18 | 15 | I | Coast (Hi-Z) all six
MOSFETs as long as DRVOFF is high. If DRVOFF pin is not used, connect to AGND directly. If DRVOFF pin is to be used for instantly coasting (Hi-Z) the MOSFETs, use an external 10-kΩ pull-down resistor (to AGND) for better noise rejection. |
DVDD | 1 | 32 | 2 | PWR | 1.5-V internal regulator output. Connect a X5R or X7R, 2.2-µF, 6.3-V ceramic capacitor between the DVDD and DGND pins. |
EXT_CLK | 33 | 26 | 23 | I | External clock reference input in external clock reference mode. |
EXT_WD | 32 | 25 | 22 | I | External watchdog input. |
FB_BK | 3 | 2 | 4 | PWR I/O | Feedback for buck regulator output control. Connect to buck regulator output after the inductor/resistor. |
FG | 29 | 22 | 19 | O | Motor speed indicator : open-drain output that requires an external pull-up resistor to 1.8-V to 5.0-V. An optional internal pull-up resistor to AVDD is enabled by setting PULLUP_ENABLE to 1b; no external pull-up resistor should be used when internal pull-up resistor is enabled. |
GND_BK | 4 | 3 | 5 | GND | Buck regulator ground. Refer Layout Guidelines for connection recommendation. |
NC | 22, 23, 24, 25 | - | - | - | No connection. Leave these pins floating or connect to Thermal pad for better heat dissipation. |
nFAULT | 40 | 31 | 1 | O | Fault indicator. Pulled logic-low during fault condition; open-drain output that requires an external pull-up resistor to 1.8-V to 5.0-V. An optional internal pull-up resistor to AVDD is enabled by setting PULLUP_ENABLE to 1b; no external pull-up resistor should be used when internal pull-up resistor is enabled. |
OUTA | 13, 14 | 11, 12 | 12 | PWR O | Half-bridge output A |
OUTB | 16, 17 | 13, 14 | 13 | PWR O | Half-bridge output B |
OUTC | 19, 20 | 15, 16 | 14 | PWR O | Half-bridge output C |
PGND | 12, 15, 18 | 10, 17 | 11 | GND | Device power ground. Refer Layout Guidelines for connection recommendation. |
SCL | 31 | 24 | 21 | I | I2C clock input |
SDA | 30 | 23 | 20 | I/O | I2C data line |
SPEED/WAKE | 28 | 21 | 18 | I | Device speed input; supports analog, PWM or frequency based speed input. The speed pin input can be configured through SPEED_MODE. |
SW_BK | 5 | 4 | 6 | PWR | Buck switch node. Connect this pin to an inductor or resistor. |
VM | 9, 10, 11 | 8, 9 | 10 | PWR I | Device and motor power supply. Connect to motor supply voltage; bypass to PGND with one 0.1-µF capacitor plus one bulk capacitor. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device. |
Thermal pad | GND | Must be connected to AGND. |