JAJSST7 January 2024 MCF8315C-Q1
PRODUCTION DATA
Table 6-34 lists the memory-mapped registers for the Hardware_Configuration registers. All register offset addresses not listed in Table 6-34 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
A4h | PIN_CONFIG | Hardware Pin Configuration | Section 6.7.3.1 |
A6h | DEVICE_CONFIG1 | Device configuration1 | Section 6.7.3.2 |
A8h | DEVICE_CONFIG2 | Device configuration2 | Section 6.7.3.3 |
AAh | PERI_CONFIG1 | Peripheral Configuration1 | Section 6.7.3.4 |
ACh | GD_CONFIG1 | Gate Driver Configuration1 | Section 6.7.3.5 |
AEh | GD_CONFIG2 | Gate Driver Configuration2 | Section 6.7.3.6 |
Complex bit access types are encoded to fit into small table cells. Table 6-35 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
W1C | W 1C | Write 1 to clear |
Reset or Default Value | ||
-n | Value after reset or the default value |
PIN_CONFIG is shown in Figure 6-74 and described in Table 6-36.
Return to the Summary Table.
Register to configure hardware pins
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | VDC_FILT_DIS | RESERVED | ||||
R-0h | R-0h | R/W-0h | R-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | FG_IDLE_CONFIG | FG_FAULT_CONFIG | ||||
R-0h | R-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FG_FAULT_CONFIG | ALARM_PIN_EN | RESERVED | RESERVED | BRAKE_INPUT | SPEED_MODE | ||
R/W-0h | R/W-0h | R-0h | R-0h | R/W-0h | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R | 0h | Reserved |
30-28 | RESERVED | R | 0h | Reserved |
27 | VDC_FILT_DIS | R/W | 0h | Vdc filter disable
0h = Enable 1h = Disable |
26-13 | RESERVED | R | 0h | Reserved |
12-11 | RESERVED | R | 0h | Reserved |
10-9 | FG_IDLE_CONFIG | R/W | 0h | FG configuration during motor stopped/idle state
0h = FG continues and end state depends on FG_CONFIG and last state before motor stops 1h = FG is pulled High 2h = FG is pulled Low 3h = FG is pulled High |
8-7 | FG_FAULT_CONFIG | R/W | 0h | FG configuration during fault state
0h = Use last FG signal when motor is driving 1h = FG is pulled High 2h = FG is pulled Low |
6 | ALARM_PIN_EN | R/W | 0h | Alarm pin enable
0h = Disable 1h = Enable |
5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R | 0h | Reserved |
3-2 | BRAKE_INPUT | R/W | 0h | Brake pin override
0h = Hardware pin (BRAKE) 1h = Override pin and apply low-side brake 2h = Override pin and do not brake 3h = Hardware pin (BRAKE) |
1-0 | SPEED_MODE | R/W | 0h | Configure input reference mode from SPEED pin
0h = Controlled by amplitude of SPEED pin (analog mode) 1h = Controlled by duty cycle of SPEED pin (PWM mode) 2h = Controlled by DIGITAL_SPEED_CTRL register (I2C mode) 3h = Controlled by frequency of SPEED pin (freq. mode) |
DEVICE_CONFIG1 is shown in Figure 6-75 and described in Table 6-37.
Return to the Summary Table.
Register to configure device
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | DAC_SOx_SEL | DAC_ENABLE | I2C_TARGET_ADDR | |||
R-0h | R-0h | R/W-0h | R/W-0h | R/W-X | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
I2C_TARGET_ADDR | RESERVED | ||||||
R/W-X | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLEW_RATE_I2C_PINS | PULLUP_ENABLE | BUS_VOLT | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R | 0h | Reserved |
30 | RESERVED | R | 0h | Reserved |
29-28 | DAC_SOx_SEL | R/W | 0h | Pin 38 configuration
0h = DACOUT2 1h = SOA 2h = SOB 3h = SOC |
27 | DAC_ENABLE | R/W | 0h | DAC enable
0h = DACOUT disabled 1h = DACOUT enabled |
26-20 | I2C_TARGET_ADDR | R/W | X | I2C target address |
19-5 | RESERVED | R | 0h | Reserved |
4-3 | SLEW_RATE_I2C_PINS | R/W | 0h | Slew rate control for I2C pins
0h = 4.8 mA 1h = 3.9 mA 2h = 1.86 mA 3h = 30.8 mA |
2 | PULLUP_ENABLE | R/W | 0h | Internal pull-up enable for nFAULT and FG pins
0h = Disable 1h = Enable |
1-0 | BUS_VOLT | R/W | 0h | Maximum DC bus voltage configuration
0h = 15 V 1h = 30 V 2h = 60 V 3h = Reserved |
DEVICE_CONFIG2 is shown in Figure 6-76 and described in Table 6-38.
Return to the Summary Table.
Register to configure device
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | INPUT_MAXIMUM_FREQ | ||||||
R-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
INPUT_MAXIMUM_FREQ | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SLEEP_ENTRY_TIME | DYNAMIC_CSA_GAIN_EN | DYNAMIC_VOLTAGE_GAIN_EN | DEV_MODE | CLK_SEL | EXT_CLK_EN | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXT_CLK_CONFIG | EXT_WDT_EN | EXT_WDT_CONFIG | EXT_WDT_INPUT_MODE | EXT_WDT_FAULT_MODE | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R | 0h | Reserved |
30-16 | INPUT_MAXIMUM_FREQ | R/W | 0h | Input frequency on speed pin for input reference mode as "controlled by frequency of SPEED pin" that corresponds to 100% duty cycle. Duty cycle = Input frequency / INPUT_MAXIMUM_FREQ |
15-14 | SLEEP_ENTRY_TIME | R/W | 0h | Device enters sleep mode when SPEED input is held continuously below threshold for SLEEP_ENTRY_TIME
0h = Sleep Entry when SPEED pin remains low for 50 µs 1h = Sleep Entry when SPEED pin remains low for 200 µs 2h = Sleep Entry when SPEED pin remains low for 20 ms 3h = Sleep Entry when SPEED pin remains low for 200 ms |
13 | DYNAMIC_CSA_GAIN_EN | R/W | 0h | Adjust CSA gain automatically for optimal current resolution at all current levels
0h = Disable 1h = Enable |
12 | DYNAMIC_VOLTAGE_GAIN_EN | R/W | 0h | Adjust voltage gain automatically for optimal voltage resolution at all voltage levels
0h = Disable 1h = Enable |
11 | DEV_MODE | R/W | 0h | Device mode select
0h = Standby Mode 1h = Sleep Mode |
10-9 | CLK_SEL | R/W | 0h | Clock source
0h = Internal oscillator 1h = Reserved 2h = Reserved 3h = External clock input |
8 | EXT_CLK_EN | R/W | 0h | Enable external clock mode
0h = Disable 1h = Enable |
7-5 | EXT_CLK_CONFIG | R/W | 0h | External Clock Configuration
0h = 8 kHz 1h = 16 kHz 2h = 32 kHz 3h = 64 kHz 4h = 128 kHz 5h = 256 kHz 6h = 512 kHz 7h = 1024 kHz |
4 | EXT_WDT_EN | R/W | 0h | Enable external watchdog
0h = Disable 1h = Enable |
3-2 | EXT_WDT_CONFIG | R/W | 0h | Time between watchdog tickles (GPIO/I2C)
0h = 100ms/1s 1h = 200ms/2s 2h = 500ms/3s 3h = 1000ms/10s |
1 | EXT_WDT_INPUT_MODE | R/W | 0h | External watchdog input source
0h = Watchdog tickle over I2C 1h = Watchdog tickle over GPIO |
0 | EXT_WDT_FAULT_MODE | R/W | 0h | External watchdog fault mode
0h = Report only 1h = Latch with MOSFETs in Hi-Z |
PERI_CONFIG1 is shown in Figure 6-77 and described in Table 6-39.
Return to the Summary Table.
Register to peripheral1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | SPREAD_SPECTRUM_MODULATION_DIS | RESERVED | BUS_CURRENT_LIMIT | ||||
R-0h | R/W-1h | R-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUS_CURRENT_LIMIT | BUS_CURRENT_LIMIT_ENABLE | DIR_INPUT | DIR_CHANGE_MODE | RESERVED | ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY | ACTIVE_BRAKE_MOD_INDEX_LIMIT | SPEED_RANGE_SEL | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R | 0h | Reserved |
30 | SPREAD_SPECTRUM_MODULATION_DIS | R/W | 1h | Spread spectrum modulation disable
0h = SSM is enabled 1h = SSM is disabled |
29-26 | RESERVED | R | 0h | Reserved |
25-22 | BUS_CURRENT_LIMIT | R/W | 0h | Bus current limit
0h = 0.078125 A 1h = 0.15625 A 2h = 0.3125 A 3h = 0.625 A 4h = 0.9375 A 5h = 1.25 A 6h = 1.5625 A 7h = 1.875 A 8h = 2.1875 A 9h = 2.5 A Ah = 2.8125 A Bh = 3.125 A Ch = 3.4375 A Dh = 3.75 A Eh = 4.375 A Fh = 5.0 A |
21 | BUS_CURRENT_LIMIT_ENABLE | R/W | 0h | Bus current limit enable
0h = Disable 1h = Enable |
20-19 | DIR_INPUT | R/W | 0h | DIR pin override
0h = Hardware pin (DIR) 1h = Override DIR pin with clockwise rotation OUTA-OUTB-OUTC 2h = Override DIR pin with counter clockwise rotation OUTA-OUTC-OUTB 3h = Hardware pin (DIR) |
18 | DIR_CHANGE_MODE | R/W | 0h | Response to change of DIR pin status
0h = Follow motor stop options and ISD routine on detecting DIR change 1h = Change the direction through reverse drive while continuously driving the motor |
17 | RESERVED | R | 0h | Reserved |
16-13 | ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY | R/W | 0h | Difference between final speed and present speed below which active braking will be applied
0h = reserved 1h = 5% 2h = 10% 3h = 15% 4h = 20% 5h = 25% 6h = 30% 7h = 35% 8h = 40% 9h = 45% Ah = 50% Bh = 60% Ch = 70% Dh = 80% Eh = 90% Fh = 100% |
12-10 | ACTIVE_BRAKE_MOD_INDEX_LIMIT | R/W | 0h | Modulation index limit below which active braking will be applied
0h = 0% 1h = 40% 2h = 50% 3h = 60% 4h = 70% 5h = 80% 6h = 90% 7h = 100% |
9 | SPEED_RANGE_SEL | R/W | 0h | Frequency range selection for PWM duty mode reference input
0h = 325Hz to 100kHz 1h = 10Hz to 325Hz |
8 | RESERVED | R | 0h | Reserved |
7-0 | RESERVED | R | 0h | Reserved |
GD_CONFIG1 is shown in Figure 6-78 and described in Table 6-40.
Return to the Summary Table.
Register to configure gated driver settings1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PARITY | RESERVED | RESERVED | SLEW_RATE | RESERVED | |||
R/W-0h | R-0h | R-0h | R/W-0h | R-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | OVP_SEL | OVP_EN | RESERVED | RESERVED |
R-0h | R-0h | R-0h | R-0h | R/W-0h | R/W-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | OCP_DEG | RESERVED | OCP_LVL | OCP_MODE | ||
R-0h | R-0h | R/W-0h | R-0h | R/W-0h | R/W-1h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | CSA_GAIN | |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PARITY | R/W | 0h | Parity bit |
30-29 | RESERVED | R | 0h | Reserved |
28 | RESERVED | R | 0h | Reserved |
27-26 | SLEW_RATE | R/W | 0h | Slew rate
0h = Reserved 1h = Reserved 2h = Slew rate is 125 V/µs 3h = Slew rate is 200 V/µs |
25-24 | RESERVED | R | 0h | Reserved |
23 | RESERVED | R | 0h | Reserved |
22 | RESERVED | R | 0h | Reserved |
21 | RESERVED | R | 0h | Reserved |
20 | RESERVED | R | 0h | Reserved |
19 | OVP_SEL | R/W | 0h | Overvoltage level
0h = VM overvoltage level is 34-V 1h = VM overvoltage level is 22-V |
18 | OVP_EN | R/W | 0h | Overvoltage enable
0h = Overvoltage protection is disabled 1h = Overvoltage protection is enabled |
17 | RESERVED | R | 0h | Reserved |
16 | RESERVED | R | 0h | Reserved |
15 | RESERVED | R | 0h | Reserved |
14 | RESERVED | R | 0h | Reserved |
13-12 | OCP_DEG | R/W | 0h | OCP deglitch time
0h = OCP deglitch time is 0.2 µs 1h = OCP deglitch time is 0.6 µs 2h = OCP deglitch time is 1.2 µs 3h = OCP deglitch time is 1.6 µs |
11 | RESERVED | R | 0h | Reserved |
10 | OCP_LVL | R/W | 0h | Overcurrent level
0h = OCP level is 9 A (Typical) 1h = OCP level is 13 A (Typical) |
9-8 | OCP_MODE | R/W | 1h | OCP fault mode
0h = Overcurrent causes a latched fault 1h = Overcurrent causes an automatic retrying fault after 500ms 2h = Reserved 3h = Reserved |
7 | RESERVED | R | 0h | Reserved |
6 | RESERVED | R | 0h | Reserved |
5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1-0 | CSA_GAIN | R/W | 0h | Current sense amplifier's gain (used only if DYNAMIC_CSA_GAIN_EN = 0)
0h = CSA gain is 0.24 V/A 1h = CSA gain is 0.48 V/A 2h = CSA gain is 0.96 V/A 3h = CSA gain is 1.92 V/A |
GD_CONFIG2 is shown in Figure 6-79 and described in Table 6-41.
Return to the Summary Table.
Register to configure gated driver settings2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PARITY | DELAY_COMP_EN | TARGET_DELAY | RESERVED | BUCK_PS_DIS | |||
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W1C-1h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BUCK_CL | BUCK_SEL | BUCK_DIS | MIN_ON_TIME | RESERVED | |||
R/W-0h | R/W-1h | R/W-0h | R/W-0h | R-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PARITY | R/W | 0h | Parity bit |
30 | DELAY_COMP_EN | R/W | 0h | Driver delay compensation enable
0h = Disable 1h = Enable |
29-26 | TARGET_DELAY | R/W | 0h | Delay target for driver delay compensation
0h = Automatic based on slew rate 1h = 0.4 µs 2h = 0.6 µs 3h = 0.8 µs 4h = 1 µs 5h = 1.2 µs 6h = 1.4 µs 7h = 1.6 µs 8h = 1.8 µs 9h = 2 µs Ah = 2.2 µs Bh = 2.4 µs Ch = 2.6 µs Dh = 2.8 µs Eh = 3 µs Fh = 3.2 µs |
25 | RESERVED | R | 0h | Reserved |
24 | BUCK_PS_DIS | R/W1C | 1h | Buck power sequencing disable
0h = Buck power sequencing is enabled 1h = Buck power sequencing is disabled |
23 | BUCK_CL | R/W | 0h | Buck current limit
0h = Buck regulator current limit is set to 600 mA 1h = Buck regulator current limit is set to 150 mA |
22-21 | BUCK_SEL | R/W | 1h | Buck output voltage
0h = Buck voltage is 3.3 V 1h = Buck voltage is 5.0 V 2h = Buck voltage is 4.0 V 3h = Buck voltage is 5.7 V |
20 | BUCK_DIS | R/W | 0h | Buck disable
0h = Buck regulator is enabled 1h = Buck regulator is disabled |
19-17 | MIN_ON_TIME | R/W | 0h | Minimum ON time for low side MOSFET
0h = 0 µs 1h = Automatic based on slew rate 2h = 0.5 µs 3h = 0.75 µs 4h = 1 µs 5h = 1.25 µs 6h = 1.5 µs 7h = 2 µs |
16-0 | RESERVED | R | 0h | Reserved |