JAJSNT0A december 2022 – april 2023 MCT8315A
PRODUCTION DATA
When an OCP event happens in this mode, all the FETs are disabled and the nFAULT pin is driven low. The DRIVER_FAULT, OCP and corresponding FET's OCP bits are set to 1b in the fault status registers. Normal operation resumes automatically (gate driver operation and the nFAULT pin is released) after the tRETRY (OCP_RETRY) time elapses. The DRIVER_FAULT bit is reset to 0b after the tRETRY period expires. The OCP and corresponding FET's OCP bits are set to 1b until cleared through the CLR_FLT bit.