JAJSJ40M June   2007  – March 2022 MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Typical Characteristics – Active Mode Supply Current (Into VCC)
    6. 8.6  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 8.7  Typical Characteristics – LPM4 Current
    8. 8.8  Schmitt-Trigger Inputs (Ports P1 to P8, RST/NMI, JTAG, XIN, and XT2IN)
    9. 8.9  Inputs (Ports P1 and P2)
    10. 8.10 Leakage Current (Ports P1 to P8)
    11. 8.11 Standard Inputs ( RST/NMI)
    12. 8.12 Outputs (Ports P1 to P8)
    13. 8.13 Output Frequency (Ports P1 to P8)
    14. 8.14 Typical Characteristics – Outputs
    15. 8.15 POR and Brownout Reset (BOR)
    16. 8.16 Typical Characteristics – POR and BOR
    17. 8.17 Supply Voltage Supervisor (SVS), Supply Voltage Monitor (SVM)
    18. 8.18 Main DCO Characteristics
    19. 8.19 DCO Frequency
    20. 8.20 Calibrated DCO Frequencies – Tolerance at Calibration
    21. 8.21 Calibrated DCO Frequencies – Tolerance Over Temperature 0°C to 85°C
    22. 8.22 Calibrated DCO Frequencies – Tolerance Over Supply Voltage VCC
    23. 8.23 Calibrated DCO Frequencies – Overall Tolerance
    24. 8.24 Typical Characteristics – Calibrated DCO Frequency
    25. 8.25 Wake-up Times From Lower-Power Modes (LPM3, LPM4)
    26. 8.26 Typical Characteristics – DCO Clock Wake-up Time From LPM3 or LPM4
    27. 8.27 DCO With External Resistor ROSC
    28. 8.28 Typical Characteristics – DCO With External Resistor ROSC
    29. 8.29 Crystal Oscillator LFXT1, Low-Frequency Mode
    30. 8.30 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    31. 8.31 Crystal Oscillator LFXT1, High-Frequency Mode
    32. 8.32 Typical Characteristics – LFXT1 Oscillator in HF Mode (XTS = 1)
    33. 8.33 Crystal Oscillator XT2
    34. 8.34 Typical Characteristics – XT2 Oscillator
    35. 8.35 Timer_A
    36. 8.36 Timer_B
    37. 8.37 USCI (UART Mode)
    38. 8.38 USCI (SPI Master Mode)
    39. 8.39 USCI (SPI Slave Mode)
    40. 8.40 USCI (I2C Mode)
    41. 8.41 Comparator_A+
    42. 8.42 Typical Characteristics – Comparator_A+
    43. 8.43 12-Bit ADC Power Supply and Input Range Conditions
    44. 8.44 12-Bit ADC External Reference
    45. 8.45 12-Bit ADC Built-In Reference
    46. 8.46 12-Bit ADC Timing Parameters
    47. 8.47 12-Bit ADC Linearity Parameters
    48. 8.48 12-Bit ADC Temperature Sensor and Built-In VMID
    49. 8.49 12-Bit DAC Supply Specifications
    50. 8.50 12-Bit DAC Linearity Specifications
    51. 8.51 Typical Characteristics, 12-Bit DAC Linearity Specifications
    52. 8.52 12-Bit DAC Output Specifications
    53. 8.53 12-Bit DAC Reference Input Specifications
    54. 8.54 12-Bit DAC Dynamic Specifications
    55. 8.55 Flash Memory
    56. 8.56 RAM
    57. 8.57 JTAG Interface
    58. 8.58 JTAG Fuse
  9. 9 Detailed Description
    1. 9.1  CPU
    2. 9.2  Instruction Set
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Special Function Registers (SFRs)
    6. 9.6  Memory Organization
    7. 9.7  Bootloader (BSL)
    8. 9.8  Flash Memory
    9. 9.9  Peripherals
      1. 9.9.1  DMA Controller (MSP430F261x Only)
      2. 9.9.2  Oscillator and System Clock
      3. 9.9.3  Calibration Data Stored in Information Memory Segment A
      4. 9.9.4  Brownout, Supply Voltage Supervisor (SVS)
      5. 9.9.5  Digital I/O
      6. 9.9.6  Watchdog Timer (WDT+)
      7. 9.9.7  Hardware Multiplier
      8. 9.9.8  Universal Serial Communication Interface (USCI)
      9. 9.9.9  Timer_A3
      10. 9.9.10 Timer_B7
      11. 9.9.11 Comparator_A+
      12. 9.9.12 ADC12
      13. 9.9.13 DAC12 (MSP430F261x Only)
      14. 9.9.14 Peripheral File Map
    10. 9.10 Port Diagrams
      1. 9.10.1  Port P1 (P1.0 to P1.7), Input/Output With Schmitt Trigger
      2. 9.10.2  Port P2 (P2.0 to P2.4, P2.6, and P2.7), Input/Output With Schmitt Trigger
      3. 9.10.3  Port P2 (P2.5), Input/Output With Schmitt Trigger
      4. 9.10.4  Port P3 (P3.0 to P3.7), Input/Output With Schmitt Trigger
      5. 9.10.5  Port P4 (P4.0 to P4.7), Input/Output With Schmitt Trigger
      6. 9.10.6  Port P5 (P5.0 to P5.7), Input/Output With Schmitt Trigger
      7. 9.10.7  Port P6 (P6.0 to P6.4), Input/Output With Schmitt Trigger
      8. 9.10.8  Port P6 (P6.5 and P6.6), Input/Output With Schmitt Trigger
      9. 9.10.9  Port P6 (P6.7), Input/Output With Schmitt Trigger
      10. 9.10.10 Port P7 (P7.0 to P7.7), Input/Output With Schmitt Trigger
      11. 9.10.11 Port P8 (P8.0 to P8.5), Input/Output With Schmitt Trigger
      12. 9.10.12 Port P8 (P8.6), Input/Output With Schmitt Trigger
      13. 9.10.13 Port P8 (P8.7), Input/Output With Schmitt Trigger
      14. 9.10.14 JTAG Pins (TMS, TCK, TDI/TCLK, TDO/TDI) Input/Output With Schmitt Trigger
      15. 9.10.15 JTAG Fuse Check Mode
  10. 10Device and Documentation Support
    1. 10.1 Getting Started
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Revision History

Changes from revision L to revision M

Changes from May 2, 2020 to March 31, 2022

  • 文書全体にわたって表、図、相互参照の採番方法を更新Go
  • Changed the fADC12CLK MAX value to 7 MHz in Section 8.46 12-Bit ADC Timing Parameters Go
  • Changed the fADC12OSC MAX value to 7 MHz in Section 8.46 12-Bit ADC Timing Parameters Go
  • Changed the tCONVERT MIN value to 1.86 μs in Section 8.46 12-Bit ADC Timing Parameters Go
  • Removed ADC12DIV from the formula for the TYP value of conversion time because ADC12CLK is after this division in Section 8.46 12-Bit ADC Timing Parameters Go
  • Added a link to additional information in Section 9.7, Bootloader (BSL) Go
  • Updated Section 10.5, Support Resources Go

Changes from revision K to revision L

Changes from November 9, 2012 to May 1, 2020

  • ドキュメント全体を通してフォーマットを変更、セクション番号の追加も含むGo
  • ドキュメント全体を通して、 ZCA パッケージを追加Go
  • 製品情報の表を追加Go
  • ZQW パッケージで注文可能なすべての型番のステータスを変更Go
  • Section 4を追加し、機能ブロック図をこのセクションに移動Go
  • Added Section 6, Device Comparison Go
  • Added Section 8 and moved all electrical specifications to itGo
  • Added Section 8.2, ESD Ratings Go
  • Removed "I version" row from TA row in Section 8.3 (all available devices are "T version" temperature range)Go
  • Added separate rows for Information memory segments to Table 9-8, Memory Organization Go
  • Changed all instances of "bootstrap loader" to "bootloader"Go
  • Changed all instances of "INCHx = 0x1010" to "INCHx = 1010b", and corrected all values in the ADDRESS OFFSET column in Table 9-11, Labels Used by the ADC Calibration Tags Go
  • Corrected P4DIR.x value (changed from 1 to 0) for Timer_B7.TBCLK entry in Table 9-19, Port P4 (P4.0 to P4.7) Pin Functions Go
  • Added Section 10 and moved Trademarks and Electrostatic Discharge Caution sections to itGo
  • Added Section 11, Mechanical, Packaging, and Orderable Information Go

Changes from initial release to revision K

REVISION COMMENTS
SLAS541K
November 2012		 Changed P8.6/XT2OUT and P8.7/XT2IN to I/O in Signal Descriptions
SLAS541J
December 2011		 Added nonmagnetic package option
SLAS541I
July 2011		 Changed Tstg, Programmed device, to -55°C to 150°C in Section 1
SLAS541H
May 2011

Changed Control Bits/Signals in Table 1-1, Table 1-1, and Table 1-1

Changed crystal signal names in Table 1-1 and Table 1-1

SLAS541G
March 2011		 Changed limits on td(SVSon) parameter
SLAS541F
December 2009

Renamed Tags Used by the ADC Calibration Tags table to Tags used by the TLV Structure

Changed value of TAG_ADC12_1 from 0x10 to 0x08 in Tags used by the TLV Structure

Added CAOUT to P1.0/TACLK, Changed Timer_A3.CCI0A to Timer_A3.CCI1A and Timer_A3.TA0 to Timer_A3.TA1 in P1.2/TA1 row, Changed Timer_A3.CCI0A to Timer_A3.CCI2A and Timer_A3.TA0 to Timer_A3.TA2 in P1.3/TA2 row in Port P1 (P1.0 to P1.7) pin functions table

Changed TA0 to Timer_A3.CCI0B in P2.2/CAOUT/TA0/CA4 row of Port P2.0, P2.3, P2.4, P2.6 and P2.7 pin functions table
SLAS541E
January 2009

Corrected LFXT1Sx values in Figures 23 and 24

Corrected XT2Sx values in Figures 25 and 26

Corrected tCMErase MIN value from 200 ms to 20 ms and removed two notes in the flash memory table
SLAS541D
November 2008

Added the ESD disclaimer

Added reserved BGA pins to the terminal function list

Corrected the references in the output port parameters

Corrected the cumulative program time of the flash
SLAS541C
June 2008		 Release to market of MSP430F261x BGA devices
SLAS541B
May 2008		 Added preview of MSP430F261x BGA devices
SLAS541A
October 2007

PRODUCTION DATA release

Corrected the format and the content shown on the first page

Corrected pin number of P3.6 and P3.7 in 64-pin package in the terminal function list

Corrected the port schematics

Corrected "calibration data" section: typos and formatting corrected

Added the figure "typical characteristics - LPM4 current"
SLAS541
June 2007		 PRODUCT PREVIEW release

Changes from Revision () to Revision ()