JAJS274B April 2004 – November 2016 MSP430F423 , MSP430F425 , MSP430F427
PRODUCTION DATA.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Voltage applied at VCC to VSS | –0.3 | 4.1 | V | ||
Voltage applied to any pin(2) | –0.3 | VCC + 0.3 | V | ||
Diode current at any device terminal | ±2 | mA | |||
Storage temperature range, Tstg | Unprogrammed device | –55 | 150 | °C | |
Programmed device | –40 | 85 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±1000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±250 |
MIN | NOM | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
VCC | Supply voltage during program execution(1) (AVCC = DVCC = VCC) | SD16 disabled | 1.8 | 3.6 | V | ||
SVS enabled, PORON = 1(2), SD16 disabled | 2.0 | 3.6 | |||||
SD16 enabled or during programming of flash memory | 2.7 | 3.6 | |||||
VSS | Supply voltage (AVSS = DVSS = VSS) | 0 | 0 | V | |||
TA | Operating free-air temperature range | –40 | 85 | °C | |||
f(LFXT1) | LFXT1 crystal frequency(3) | LF selected, XTS_FLL = 0 | Watch crystal | 32.768 | kHz | ||
XT1 selected, XTS_FLL = 1 | Ceramic resonator | 450 | 8000 | ||||
XT1 selected, XTS_FLL = 1 | Crystal | 1000 | 8000 | ||||
f(System) | Processor frequency (signal MCLK) (also see Figure 5-1) | VCC = 1.8 V | DC | 4.15 | MHz | ||
VCC = 3.6 V | DC | 8 |
PARAMETER | TA | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
I(AM) | Active mode (AM) f(MCLK) = f(SMCLK) = f(DCO) = 1 MHz, f(ACLK) = 32768 Hz, XTS_FLL = 0, program executes in flash |
–40°C to 85°C | 3 V | 400 | 500 | µA | |
I(LPM0) | Low-power mode 0 or 1 (LPM0 or LPM1)(2)
f(MCLK) = f(SMCLK) = f(DCO) = 1 MHz, f(ACLK) = 32768 Hz, XTS_FLL = 0, FN_8 = FN_4 = FN_3 = FN_2 = 0 |
–40°C to 85°C | 3 V | 130 | 150 | µA | |
I(LPM2) | Low-power mode 2 (LPM2)(2) | –40°C to 85°C | 3 V | 10 | 22 | µA | |
I(LPM3) | Low-power mode 3 (LPM3) (2) | –40°C | 3 V | 1.5 | 2.0 | µA | |
25°C | 1.6 | 2.1 | |||||
60°C | 1.7 | 2.2 | |||||
85°C | 2.0 | 3.5 | |||||
I(LPM4) | Low-power mode 4 (LPM4)(2) | –40°C | 3 V | 0.1 | 0.5 | µA | |
25°C | 0.1 | 0.5 | |||||
85°C | 0.8 | 2.5 |
Current consumption of active mode versus system frequency:
I(AM) = I(AM) [at 1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage:
I(AM) = I(AM) [at 3 V] + 170 µA/V × (VCC – 3 V)
PARAMETER | VALUE | UNIT | |
---|---|---|---|
RθJA | Junction-to-ambient thermal resistance, still air(1) | 55.7 | °C/W |
RθJC(TOP) | Junction-to-case (top) thermal resistance(2) | 16.7 | °C/W |
RθJB | Junction-to-board thermal resistance(3) | 27.1 | °C/W |
ΨJB | Junction-to-board thermal characterization parameter | 26.8 | °C/W |
ΨJT | Junction-to-top thermal characterization parameter | 0.8 | °C/W |
PARAMETER | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|
VIT+ | Positive-going input threshold voltage | 3 V | 1.5 | 1.98 | V |
VIT- | Negative-going input threshold voltage | 3 V | 0.9 | 1.3 | V |
Vhys | Input voltage hysteresis (VIT+ - VIT- ) | 3 V | 0.45 | 1 | V |
PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
t(int) | External interrupt timing | Port P1, P2: P1.x to P2.x, external trigger signal for the interrupt flag(1) | 3 V | 1.5 | cycle | |
50 | ns | |||||
t(cap) | Timer_A capture timing | TAx | 3 V | 50 | ns | |
f(TAext) | Timer_A clock frequency externally applied to pin | TAxCLK, INCLK t(H) = t(L) | 3 V | 10 | MHz | |
f(TAint) | Timer_A clock frequency | SMCLK or ACLK signal selected | 3 V | 10 | MHz |
PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
Ilkg(P1.x) | Leakage current, Port P1.x | Port 1: V(P1.x) (2) | 3 V | ±50 | nA | |
Ilkg(P2.x) | Leakage current, Port P2.x | Port 2: V(P2.x) (2) | 3 V | ±50 | nA |
PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH(max) = –1.5 mA(1) | 3 V | VCC – 0.25 | VCC | V |
IOH(max) = –6 mA(2) | 3 V | VCC – 0.6 | VCC | |||
VOL | Low-level output voltage | IOL(max) = 1.5 mA(1) | 3 V | VSS | VSS + 0.25 | V |
IOL(max) = 6 mA(2) | 3 V | VSS | VSS + 0.6 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
f(Px.y) | Output frequency (1 ≤ × ≤ 2, 0 ≤ y ≤ 7) |
CL = 20 F, IL = ±1.5 mA, VCC = 3 V | DC | 12 | MHz | ||
f(ACLK), | P1.1/TA0/MCLK, P1.5/TACLK/ACLK/S28 |
CL = 20 pF, VCC = 3 V | 12 | MHz | |||
f(MCLK), | |||||||
f(SMCLK) | |||||||
t(Xdc) | Duty cycle of output frequency | P1.5/TACLK/ACLK/S28, CL = 20 pF, VCC = 3 V |
fACLK = fLFXT1 = fXT1 | 40% | 60% | ||
fACLK = fLFXT1 = fLF | 30% | 70% | |||||
fACLK = fLFXT1 | 50% | ||||||
P1.1/TA0/MCLK, CL = 20 pF, VCC = 3 V, fMCLK = fDCOCLK |
50% – 15 ns | 50% | 50% + 15 ns |
Figure 5-2 through Figure 5-5 show the typical output currents of Ports P1 and P2. One output loaded at a time.
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
td(LPM3) | Delay time | f = 1 MHz | VCC = 3 V | 6 | µs | |
f = 2 MHz | 6 | |||||
f = 3 MHz | 6 |
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
VRAMh | CPU halted(1) | 1.6 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
V(33) | Analog voltage | Voltage at R33 | VCC = 3 V | 2.5 | VCC + 0.2 | V | |
V(23) | Voltage at R23 | [V(33) – V(03)] × 2/3 + V(03) | |||||
V(13) | Voltage at R13 | [V(33) – V(03)] × 1/3 + V(03) | |||||
V(33) – V(03) | Voltage at R33 to R03 | 2.5 | VCC + 0.2 | ||||
I(R03) | Input leakage | R03 = VSS | No load at all segment and common lines, VCC = 3 V |
±20 | nA | ||
I(R13) | R13 = VCC / 3 | ±20 | |||||
I(R23) | R23 = 2 × VCC / 3 | ±20 | |||||
V(Sxx0) | Segment line voltage | I(Sxx) = –3 µA, VCC = 3 V | V(03) | V(03) – 0.1 | V | ||
V(Sxx1) | V(13) | V(13) – 0.1 | |||||
V(Sxx2) | V(23) | V(23) – 0.1 | |||||
V(Sxx3) | V(33) | V(33) + 0.1 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
t(τ) | USART0 deglitch time | VCC = 3 V, SYNC = 0, UART mode | 150 | 280 | 500 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
td(BOR) | Brownout(2) | 2000 | µs | |||
VCC(start) | dVCC/dt ≤ 3 V/s (see Figure 5-6) | 0.7 × V(B_IT– ) | V | |||
V(B_IT–) | dVCC/dt ≤ 3 V/s (see Figure 5-6 through Figure 5-8) | 1.71 | V | |||
Vhys(B_IT–) | dVCC/dt ≤ 3 V/s (see Figure 5-6) | 70 | 130 | 180 | mV | |
t(reset) | Pulse duration needed at RST/NMI pin to accept reset internally, VCC = 3 V | 2 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
t(SVSR) | dVCC/dt > 30 V/ms (see Figure 5-9) | 5 | 150 | µs | ||
dVCC/dt ≤ 30 V/ms | 2000 | |||||
td(SVSon) | SVS on, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V | 20 | 150 | µs | ||
tsettle | VLD ≠ 0(2) | 12 | µs | |||
V(SVSstart) | VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 5-9) | 1.55 | 1.7 | V | ||
Vhys(SVS_IT–) | VCC/dt ≤ 3 V/s (see Figure 5-9) | VLD = 1 | 70 | 120 | 155 | mV |
VLD = 2 to 14 | V(SVS_IT–) × 0.004 | V(SVS_IT–) × 0.008 | ||||
VCC/dt ≤ 3 V/s (see Figure 5-9), external voltage applied on P2.3 | VLD = 15 | 4.4 | 10.4 | mV | ||
V(SVS_IT–) | VCC/dt ≤ 3 V/s (see Figure 5-9) | VLD = 1 | 1.8 | 1.9 | 2.05 | V |
VLD = 2 | 1.94 | 2.1 | 2.25 | |||
VLD = 3 | 2.05 | 2.2 | 2.37 | |||
VLD = 4 | 2.14 | 2.3 | 2.48 | |||
VLD = 5 | 2.24 | 2.4 | 2.6 | |||
VLD = 6 | 2.33 | 2.5 | 2.71 | |||
VLD = 7 | 2.46 | 2.65 | 2.86 | |||
VLD = 8 | 2.58 | 2.8 | 3 | |||
VLD = 9 | 2.69 | 2.9 | 3.13 | |||
VLD = 10 | 2.83 | 3.05 | 3.29 | |||
VLD = 11 | 2.94 | 3.2 | 3.42 | |||
VLD = 12 | 3.11 | 3.35 | 3.61(1) | |||
VLD = 13 | 3.24 | 3.5 | 3.76(1) | |||
VLD = 14 | 3.43 | 3.7(1) | 3.99(1) | |||
VCC/dt ≤ 3 V/s (see Figure 5-9), external voltage applied on P2.3 | VLD = 15 | 1.1 | 1.2 | 1.3 | ||
ICC(SVS)(3) | VLD ≠ 0, VCC = 2.2 V or 3 V | 10 | 15 | µA |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
f(DCOCLK) | N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0, fCrystal = 32.768 kHz | 3 V | 1 | MHz | ||
f(DCO = 2) | FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1 | 3 V | 0.3 | 0.7 | 1.3 | MHz |
f(DCO = 27) | FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1 | 3 V | 2.7 | 6.1 | 11.3 | MHz |
f(DCO = 2) | FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1 | 3 V | 0.8 | 1.5 | 2.5 | MHz |
f(DCO = 27) | FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1 | 3 V | 6.5 | 12.1 | 20 | MHz |
f(DCO = 2) | FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1 | 3 V | 1.3 | 2.2 | 3.5 | MHz |
f(DCO = 27) | FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1 | 3 V | 10.3 | 17.9 | 28.5 | MHz |
f(DCO = 2) | FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1 | 3 V | 2.1 | 3.4 | 5.2 | MHz |
f(DCO = 27) | FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1 | 3 V | 16 | 26.6 | 41 | MHz |
f(DCO = 2) | FN_8 = 1, FN_4 = 1 = FN_3 = FN_2 = x, DCOPLUS = 1 | 3 V | 4.2 | 6.3 | 9.2 | MHz |
f(DCO = 27) | FN_8 = 1, FN_4 = 1 = FN_3 = FN_2 = x, DCOPLUS = 1 | 3 V | 30 | 46 | 70 | MHz |
Sn | Step size (ratio) between adjacent DCO taps: Sn = fDCO(Tap n+1)/fDCO(Tap n) (see Figure 5-12 for taps 21 to 27) |
1 < TAP ≤ 20 | 1.06 | 1.11 | ||
TAP = 27 | 1.07 | 1.17 | ||||
Dt | Temperature drift, N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0 | 3 V | –0.2 | –0.3 | –0.4 | %/°C |
DV | Drift with VCC variation, N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0 | 0 | 5 | 15 | %/V |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
CXIN | Integrated input capacitance(4) | OSCCAPx = 0h | 3 V | 0 | pF | ||
OSCCAPx = 1h | 10 | ||||||
OSCCAPx = 2h | 14 | ||||||
OSCCAPx = 3h | 18 | ||||||
CXOUT | Integrated output capacitance(4) | OSCCAPx = 0h | 3 V | 0 | pF | ||
OSCCAPx = 1h | 10 | ||||||
OSCCAPx = 2h | 14 | ||||||
OSCCAPx = 3h | 18 | ||||||
VIL | Input levels at XIN(3) | 3 V | VSS | 0.2 × VCC | V | ||
VIH | 0.8 × VCC | VCC |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
AVCC | Analog supply voltage | AVCC = DVCC, AVSS = DVSS = 0 V | 2.7 | 3.6 | V | |||
ISD16 | Analog supply current: 1 active SD16 channel including internal reference | SD16LP = 0, fSD16 = 1 MHz, SD16OSR = 256 |
GAIN: 1, 2 | 3 V | 650 | 950 | µA | |
GAIN: 4, 8, 16 | 730 | 1100 | ||||||
GAIN: 32 | 1050 | 1550 | ||||||
SD16LP = 1, fSD16 = 0.5 MHz, SD16OSR = 256 |
GAIN: 1 | 620 | 930 | |||||
GAIN: 32 | 700 | 1060 | ||||||
fSD16 | Analog front-end input clock frequency | SD16LP = 0 (low-power mode disabled) | 1 | MHz | ||||
SD16LP = 1 (low-power mode enabled) | 0.5 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VID | Differential input voltage range for specified performance(2) | SD16GAINx = 1, SD16REFON = 1 | ±500 | mV | |||
SD16GAINx = 2, SD16REFON = 1 | ±250 | ||||||
SD16GAINx = 4, SD16REFON = 1 | ±125 | ||||||
SD16GAINx = 8, SD16REFON = 1 | ±62 | ||||||
SD16GAINx = 16, SD16REFON = 1 | ±31 | ||||||
SD16GAINx = 32, SD16REFON = 1 | ±15 | ||||||
ZI | Input impedance (one input pin to AVSS) |
fSD16 = 1 MHz, SD16GAINx = 1 | 3 V | 200 | kΩ | ||
fSD16 = 1 MHz, SD16GAINx = 32 | 75 | ||||||
ZID | Differential input impedance (IN+ to IN−) |
fSD16 = 1 MHz, SD16GAINx = 1 | 3 V | 300 | 400 | kΩ | |
fSD16 = 1 MHz, SD16GAINx = 32 | 100 | 150 | |||||
VI | Absolute input voltage range | AVSS – 1 | AVCC | V | |||
VIC | Common-mode input voltage range | AVSS – 1 | AVCC | V |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
SINAD | Signal-to-noise + distortion ratio | SD16GAINx = 1, signal amplitude = 500 mV | fIN = 50 Hz or 100 Hz | 3 V | 83.5 | 85 | dB | |
SD16GAINx = 2, signal amplitude = 250 mV | 81.5 | 84 | ||||||
SD16GAINx = 4, signal amplitude = 125 mV | 76 | 79.5 | ||||||
SD16GAINx = 8, signal amplitude = 62 mV | 73 | 76.5 | ||||||
SD16GAINx = 16, signal amplitude = 31 mV | 69 | 73 | ||||||
SD16GAINx = 32, signal amplitude = 15 mV | 62 | 69 | ||||||
G | Nominal gain | SD16GAINx = 1 | 3 V | 0.97 | 1.00 | 1.02 | ||
SD16GAINx = 2 | 1.90 | 1.96 | 2.02 | |||||
SD16GAINx = 4 | 3.76 | 3.86 | 3.96 | |||||
SD16GAINx = 8 | 7.36 | 7.62 | 7.84 | |||||
SD16GAINx = 16 | 14.56 | 15.04 | 15.52 | |||||
SD16GAINx = 32 | 27.20 | 28.35 | 29.76 | |||||
EOS | Offset error | SD16GAINx = 1 | 3 V | ±0.2 | %FSR | |||
SD16GAINx = 32 | ±1.5 | |||||||
dEOS/dT | Offset error temperature coefficient | SD16GAINx = 1 | 3 V | ±4 | ±20 | ppm FSR/°C | ||
SD16GAINx = 32 | ±20 | ±100 | ||||||
CMRR | Common-mode rejection ratio | SD16GAINx = 1, Common-mode input signal: VID = 500 mV, fIN = 50 Hz or 100 Hz |
3 V | >90 | dB | |||
SD16GAINx = 32, Common-mode input signal: VID = 16 mV, fIN = 50 Hz or 100 Hz |
>75 | |||||||
AC PSRR | AC power-supply rejection ratio | SD16GAINx = 1, VCC = 3 V ±100 mV, fVCC = 50 Hz | 3 V | >80 | dB | |||
XT | Crosstalk | 3 V | <–100 | dB |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
TCSensor | Sensor temperature coefficient | 1.18 | 1.32 | 1.46 | mV/K | ||
VOffset,sensor | Sensor offset voltage | –100 | 100 | mV | |||
VSensor | Sensor output voltage(2) | Temperature sensor voltage at TA = 85°C | 3 V | 435 | 475 | 515 | mV |
Temperature sensor voltage at TA = 25°C | 355 | 395 | 435 | ||||
Temperature sensor voltage at TA = 0°C | 320 | 360 | 400 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VREF | Internal reference voltage | SD16REFON = 1, SD16VMIDON = 0 | 3 V | 1.14 | 1.20 | 1.26 | V |
IREF | Reference supply current | SD16REFON = 1, SD16VMIDON = 0 | 3 V | 175 | 260 | µA | |
TC | Temperature coefficient | SD16REFON = 1, SD16VMIDON = 0 | 3 V | 20 | 50 | ppm/K | |
CREF | VREF load capacitance | SD16REFON = 1 SD16VMIDON = 0(1) | 100 | nF | |||
ILOAD | VREF(I) maximum load current | SD16REFON = 0, SD16VMIDON = 0 | 3 V | ±200 | nA | ||
tON | Turnon time | SD16REFON = 0 → 1, SD16VMIDON = 0, CREF = 100 nF |
3 V | 5 | ms | ||
DC PSR | DC power supply rejection, ΔVREF/ΔVCC | SD16REFON = 1, SD16VMIDON = 0, VCC = 2.5 V to 3.6 V |
200 | µV/V |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VREF,BUF | Reference buffer output voltage | SD16REFON = 1, SD16VMIDON = 1 | 3 V | 1.2 | V | ||
IREF,BUF | Reference supply and reference output buffer quiescent current | SD16REFON = 1, SD16VMIDON = 1 | 3 V | 385 | 600 | A | |
CREF(O) | Required load capacitance on VREF | SD16REFON = 1, SD16VMIDON = 1 | 470 | nF | |||
ILOAD,Max | Maximum load current on VREF | SD16REFON = 1, SD16VMIDON = 1 | 3 V | ±1 | mA | ||
Maximum voltage variation versus load current | |ILOAD| = 0 to 1 mA | 3 V | –15 | +15 | mV | ||
tON | Turnon time | SD16REFON = 0 → 1, SD16VMIDON = 0, CREF = 100 nF |
3 V | 100 | µs |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VREF(I) | Input voltage | SD16REFON = 0 | 3 V | 1.0 | 1.25 | 1.5 | V |
IREF(I) | Input current | SD16REFON = 0 | 3 V | 50 | nA |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VCC(PGM/ ERASE) | Program and erase supply voltage | 2.7 | 3.6 | V | |||
fFTG | Flash timing generator frequency | 257 | 476 | kHz | |||
IPGM | Supply current from DVCC during program | 2.7 V, 3.6 V | 3 | 5 | mA | ||
IERASE | Supply current from DVCC during erase | 2.7 V, 3.6 V | 3 | 7 | mA | ||
tCPT | Cumulative program time(1) | 2.7 V, 3.6 V | 10 | ms | |||
tCMErase | Cumulative mass erase time(2) | 2.7 V, 3.6 V | 200 | ms | |||
Program and erase endurance | 104 | 105 | cycles | ||||
tRetention | Data retention duration | TJ = 25°C | 100 | years | |||
tWord | Word or byte program time(3) | 35 | tFTG | ||||
tBlock, 0 | Block program time for first byte or word(3) | 30 | |||||
tBlock, 1–63 | Block program time for each additional byte or word(3) | 21 | |||||
tBlock, End | Block program end-sequence wait time(3) | 6 | |||||
tMass Erase | Mass erase time(3) | 5297 | |||||
tSeg Erase | Segment erase time(3) | 4819 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
fTCK | TCK input frequency | See (1) | 2.2 V | 0 | 5 | MHz | |
3V | 0 | 10 | |||||
RInternal | Internal pullup resistance on TMS, TCK, TDI/TCLK | See (2) | 2.2 V, 3 V | 25 | 60 | 90 | kΩ |
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|
VCC(FB) | Supply voltage during fuse-blow condition | TA = 25°C | 2.5 | V | |
VFB | Voltage level on TDI/TCLK for fuse-blow | 6 | 7 | V | |
IFB | Supply current into TDI/TCLK during fuse blow | 100 | mA | ||
tFB | Time to blow fuse | 1 | ms |