JAJSG80 データシート

JAJSG80B May 2015 – September 2020 MSP430FG6425 , MSP430FG6426 , MSP430FG6625 , MSP430FG6626

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PZ|100
- MTQF013A

サーマルパッド・メカニカル・データ

PZ|100
- QFND428

発注情報

8.8.11.4 CTSD16, Performance

CTSD16OSRx = 256, CTSD164REFS = 1 (see Figure 8-16, Figure 8-17, and Figure 8-18)

PARAMETER		TEST CONDITIONS		V_CC	MIN	TYP	MAX	UNIT
f_M	Modulator clock					1.024		MHz
SINAD	Signal-to-noise + distortion ratio for differential inputs	CTSD16GAINx = 1, input ADx+ and ADx- (differential)	f_IN = 50 Hz⁽¹⁾	3 V	84	87		dB
		CTSD16GAINx = 2, input ADx+ and ADx- (differential)				86
		CTSD16GAINx = 4, input ADx+ and ADx- (differential)				85
		CTSD16GAINx = 8, input ADx+ and ADx- (differential)				82
		CTSD16GAINx = 16, input ADx+ and ADx- (differential)				77
SINAD	Signal-to-noise + distortion ratio for single-ended input	CTSD16GAINx = 1, input Ax (single-ended)	f_IN = 50 Hz⁽¹⁾	3 V		83		dB
		CTSD16GAINx = 2, input Ax (single-ended)				82
		CTSD16GAINx = 4, input Ax (single-ended)				78
		CTSD16GAINx = 8, input Ax (single-ended)				72
		CTSD16GAINx = 16, input Ax (single-ended)				66
G	Nominal gain	CTSD16GAINx = 1		3 V		1
		CTSD16GAINx = 2				2
		CTSD16GAINx = 4				4
		CTSD16GAINx = 8				8
		CTSD16GAINx = 16				16
E_G	Gain error	CTSD16GAINx: 1, 8, or 16 with external reference (1.2 V)		3 V	–1%		+1%
ΔE_G/ΔT	Gain error temperature coefficient, internal reference	CTSD16GAINx: 1, 8, or 16		3 V		3	50	ppm/ °C
ΔE_G/ΔT	Gain error temperature coefficient, external reference	CTSD16GAIN: 1, 8, or 16 with external reference (1.2 V)		3 V		4	15	ppm/ °C
ΔE_G/ ΔVCC	Gain error vs VCC	CTSD16GAINx: 1, 8, or 16				0.02		%/V
E_OS	Offset error	CTSD16GAINx = 1		3 V			±4.1	mV
E_OS	Offset error	CTSD16GAINx = 16		3 V			±3.4	mV
ΔEOS/ΔT	Offset error temperature coefficient	CTSD16GAINx = 1, 16		3 V		±1	±10	ppm FSR/ °C
ΔEOS/ ΔVCC	Offset error vs VCC	CTSD16GAINx = 1, 16		3 V		11		µV/V
CMRR, 50Hz	Common-mode rejection ratio at 50 Hz	CTSD16GAINx = 1, V_ID = 928 mV, f_IN = 50 Hz		3 V		78		dB
CMRR, 50Hz	Common-mode rejection ratio at 50 Hz	CTSD16GAINx = 16, V_ID = 58 mV, f_IN = 50 Hz		3 V		80		dB
AC PSRR	AC power supply rejection ratio	CTSD16GAINx: 1, V_CC = 3 V ±50 mV × sin(2π × f_Vcc × t), f_Vcc = 50 Hz, Inputs grounded (no analog signal applied)				95		dB
		CTSD16GAINx: 8, V_CC = 3 V ±50 mV × sin(2π × f_Vcc × t), f_Vcc = 50 Hz, Inputs grounded (no analog signal applied)				105
		CTSD16GAINx: 16, V_CC = 3 V ±50 mV × sin(2π × f_Vcc × t), f_Vcc = 50 Hz, Inputs grounded (no analog signal applied)				105
DC PSRR	DC power supply rejection ratio	CTSD16GAINx: (1, 8, 16), V_CC = 2.2 V to 3.6 V, (PSRR [dB] = –20 log(dVout/dVcc) with dVout observed as change in the digital conversion result; assumed to be dominated by reference)				90		dB

(1) The following voltages were applied to the CTSD16 inputs:
V_I,A+(t) = 0 V + V_PP/2 × sin(2π × f_IN × t)
V_I,A–(t) = 0 V – V_PP/2 × sin(2π × f_IN × t)
resulting in a differential voltage of V_ID = V_IN,A+(t) – V_IN,A-(t) = V_PP × sin(2π × f_IN × t) with V_PP being selected as the maximum value allowed for a given range (according to CTSD16 input range).