JAJSG80B May 2015 – September 2020 MSP430FG6425 , MSP430FG6426 , MSP430FG6625 , MSP430FG6626
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
fUSCI | USCI input clock frequency | SMCLK, ACLK, duty cycle = 50% ±10% | fSYSTEM | MHz | ||
tSU,MI | SOMI input data setup time | PMMCOREV = 0 | 1.8 V | 55 | ns | |
3 V | 38 | |||||
PMMCOREV = 3 | 2.4 V | 30 | ||||
3 V | 25 | |||||
tHD,MI | SOMI input data hold time | PMMCOREV = 0 | 1.8 V | 0 | ns | |
3 V | 0 | |||||
PMMCOREV = 3 | 2.4 V | 0 | ||||
3 V | 0 | |||||
tVALID,MO | SIMO output data valid time(2) | UCLK edge to SIMO valid, CL = 20 pF, PMMCOREV = 0 | 1.8 V | 20 | ns | |
3 V | 18 | |||||
UCLK edge to SIMO valid, CL = 20 pF, PMMCOREV = 3 | 2.4 V | 16 | ||||
3 V | 15 | |||||
tHD,MO | SIMO output data hold time(3) | CL = 20 pF, PMMCOREV = 0 | 1.8 V | –10 | ns | |
3 V | –8 | |||||
CL = 20 pF, PMMCOREV = 3 | 2.4 V | –10 | ||||
3 V | –8 |
Section 8.8.9.3 lists the characteristics of the USCI in SPI slave mode.