JAJSG80 データシート

JAJSG80B May 2015 – September 2020 MSP430FG6425 , MSP430FG6426 , MSP430FG6625 , MSP430FG6626

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PZ|100
- MTQF013A

サーマルパッド・メカニカル・データ

PZ|100
- QFND428

発注情報

9.12.2 Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2 (see Table 9-8).

Table 9-8 Port Mapping Mnemonics and Functions

VALUE	PxMAPy MNEMONIC	INPUT PIN FUNCTION	OUTPUT PIN FUNCTION
0	PM_NONE	None	DVSS
1	PM_CBOUT	–	Comparator_B output
1	PM_TB0CLK	Timer TB0 clock input	–
2	Reserved	–	Reserved
2	PM_DMAE0	DMAE0 Input	–
3	PM_SVMOUT	–	SVM output
3	PM_TB0OUTH	Timer TB0 high impedance input TB0OUTH	–
4	PM_TB0CCR0B	Timer TB0 CCR0 capture input CCI0B	Timer TB0: TB0.0 compare output Out0
5	PM_TB0CCR1B	Timer TB0 CCR1 capture input CCI1B	Timer TB0: TB0.1 compare output Out1
6	PM_TB0CCR2B	Timer TB0 CCR2 capture input CCI2B	Timer TB0: TB0.2 compare output Out2
7	PM_TB0CCR3B	Timer TB0 CCR3 capture input CCI3B	Timer TB0: TB0.3 compare output Out3
8	PM_TB0CCR4B	Timer TB0 CCR4 capture input CCI4B	Timer TB0: TB0.4 compare output Out4
9	PM_TB0CCR5B	Timer TB0 CCR5 capture input CCI5B	Timer TB0: TB0.5 compare output Out5
10	PM_TB0CCR6B	Timer TB0 CCR6 capture input CCI6B	Timer TB0: TB0.6 compare output Out6
11	PM_UCA0RXD	USCI_A0 UART RXD (Direction controlled by USCI – input)
11	PM_UCA0SOMI	USCI_A0 SPI slave out master in (direction controlled by USCI)
12	PM_UCA0TXD	USCI_A0 UART TXD (Direction controlled by USCI – output)
12	PM_UCA0SIMO	USCI_A0 SPI slave in master out (direction controlled by USCI)
13	PM_UCA0CLK	USCI_A0 clock input/output (direction controlled by USCI)
13	PM_UCB0STE	USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)
14	PM_UCB0SOMI	USCI_B0 SPI slave out master in (direction controlled by USCI)
14	PM_UCB0SCL	USCI_B0 I²C clock (open drain and direction controlled by USCI)
15	PM_UCB0SIMO	USCI_B0 SPI slave in master out (direction controlled by USCI)
15	PM_UCB0SDA	USCI_B0 I²C data (open drain and direction controlled by USCI)
16	PM_UCB0CLK	USCI_B0 clock input/output (direction controlled by USCI)
16	PM_UCA0STE	USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
17	PM_MCLK	–	MCLK
18-30	Reserved	None	DVSS
31 (0FFh)⁽¹⁾	PM_ANALOG	Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals.

(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are 5 bits wide, and the upper bits are ignored, which results in a read value of 31.

Table 9-9 lists the default settings for all pins that support port mapping.

Table 9-9 Default Mapping

PIN	PxMAPy MNEMONIC	INPUT PIN FUNCTION	OUTPUT PIN FUNCTION
P2.0/P2MAP0	PM_UCB0STE, PM_UCA0CLK	USCI_B0 SPI slave transmit enable (direction controlled by USCI – input), USCI_A0 clock input/output (direction controlled by USCI)
P2.1/P2MAP1	PM_UCB0SIMO, PM_UCB0SDA	USCI_B0 SPI slave in master out (direction controlled by USCI), USCI_B0 I²C data (open drain and direction controlled by USCI)
P2.2/P2MAP2	PM_UCB0SOMI, PM_UCB0SCL	USCI_B0 SPI slave out master in (direction controlled by USCI), USCI_B0 I²C clock (open drain and direction controlled by USCI)
P2.3/P2MAP3	PM_UCB0CLK, PM_UCA0STE	USCI_B0 clock input/output (direction controlled by USCI), USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
P2.4/P2MAP4	PM_UCA0TXD, PM_UCA0SIMO	USCI_A0 UART TXD (direction controlled by USCI – output), USCI_A0 SPI slave in master out (direction controlled by USCI)
P2.5/P2MAP5/R23	PM_UCA0RXD, PM_UCA0SOMI	USCI_A0 UART RXD (direction controlled by USCI – input), USCI_A0 SPI slave out master in (direction controlled by USCI)
P2.6/P2MAP6/R03	PM_NONE	-	DVSS
P2.7/P2MAP7/LCDREF/R13	PM_NONE	-	DVSS