JAJSEA9A
December 2017 – March 2018
MSP430FR5969-SP
PRODUCTION DATA.
1
デバイスの概要
1.1
特長
1.2
アプリケーション
1.3
概要
1.4
機能ブロック図
2
改訂履歴
3
Terminal Configuration and Functions
3.1
Pin Diagrams
3.2
Signal Descriptions
Signal Descriptions
3.3
Pin Multiplexing
3.4
Connection of Unused Pins
4
Specifications
4.1
Absolute Maximum Ratings
4.2
ESD Ratings
4.3
Recommended Operating Conditions
4.4
Active Mode Supply Current Into VCC Excluding External Current
4.5
Typical Characteristics – Active Mode Supply Currents
4.6
Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
4.7
Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
4.8
Low-Power Mode (LPM3.5, LPM4.5) Supply Currents (Into VCC) Excluding External Current
4.9
Typical Characteristics, Current Consumption per Module
4.10
Thermal Resistance Characteristics
4.11
Timing and Switching Characteristics
4.11.1
Power Supply Sequencing
Table 4-1
Brownout and Device Reset Power Ramp Requirements
Table 4-2
SVS
4.11.2
Reset Timing
Table 4-3
Reset Input
4.11.3
Clock Specifications
Table 4-4
Low-Frequency Crystal Oscillator, LFXT
Table 4-5
High-Frequency Crystal Oscillator, HFXT
Table 4-6
DCO
Table 4-7
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
Table 4-8
Module Oscillator (MODOSC)
4.11.4
Wake-up Characteristics
Table 4-9
Wake-up Times From Low-Power Modes and Reset
Table 4-10
Typical Wake-up Charge
4.11.4.1
Typical Characteristics, Average LPM Currents vs Wake-up Frequency
4.11.5
Digital I/Os
Table 4-11
Digital Inputs
Table 4-12
Digital Outputs
4.11.5.1
Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
Table 4-13
Pin-Oscillator Frequency, Ports Px
4.11.5.2
Typical Characteristics, Pin-Oscillator Frequency
4.11.6
Timer_A and Timer_B
Table 4-14
Timer_A
Table 4-15
Timer_B
4.11.7
eUSCI
Table 4-16
eUSCI (UART Mode) Clock Frequency
Table 4-17
eUSCI (UART Mode)
Table 4-18
eUSCI (SPI Master Mode) Clock Frequency
Table 4-19
eUSCI (SPI Master Mode)
Table 4-20
eUSCI (SPI Slave Mode)
Table 4-21
eUSCI (I2C Mode)
4.11.8
ADC
Table 4-22
12-Bit ADC, Power Supply and Input Range Conditions
Table 4-23
12-Bit ADC, Timing Parameters
Table 4-24
12-Bit ADC, Linearity Parameters With External Reference
Table 4-25
12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
Table 4-26
12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
Table 4-27
12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
Table 4-28
12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
Table 4-29
12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
Table 4-30
12-Bit ADC, Temperature Sensor and Built-In V1/2
Table 4-31
12-Bit ADC, External Reference
4.11.9
Reference
Table 4-32
REF, Built-In Reference
4.11.10
Comparator
Table 4-33
Comparator_E
4.11.11
FRAM
Table 4-34
FRAM
4.12
Emulation and Debug
Table 4-35
JTAG and Spy-Bi-Wire Interface
5
Detailed Description
5.1
Overview
5.2
CPU
5.3
Operating Modes
5.3.1
Peripherals in Low-Power Modes
5.3.1.1
Idle Currents of Peripherals in LPM3 and LPM4
5.4
Interrupt Vector Table and Signatures
5.5
Memory Organization
5.6
Bootloader (BSL)
5.7
JTAG Operation
5.7.1
JTAG Standard Interface
5.7.2
Spy-Bi-Wire Interface
5.8
FRAM
5.9
Memory Protection Unit Including IP Encapsulation
5.10
Peripherals
5.10.1
Digital I/O
5.10.2
Oscillator and Clock System (CS)
5.10.3
Power-Management Module (PMM)
5.10.4
Hardware Multiplier (MPY)
5.10.5
Real-Time Clock (RTC_B) (Only MSP430FR596x and MSP430FR594x)
5.10.6
Watchdog Timer (WDT_A)
5.10.7
System Module (SYS)
5.10.8
DMA Controller
5.10.9
Enhanced Universal Serial Communication Interface (eUSCI)
5.10.10
TA0, TA1
5.10.11
TA2, TA3
5.10.12
TB0
5.10.13
ADC12_B
5.10.14
Comparator_E
5.10.15
CRC16
5.10.16
AES256 Accelerator
5.10.17
True Random Seed
5.10.18
Shared Reference (REF)
5.10.19
Embedded Emulation
5.10.19.1
Embedded Emulation Module (EEM)
5.10.19.2
EnergyTrace++ Technology
5.10.20
Peripheral File Map
5.11
Input and Output Diagrams
5.11.1
Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
5.11.2
Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
5.11.3
Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
5.11.4
Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
5.11.5
Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
5.11.6
Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
5.11.7
Port P2 (P2.7) Input/Output With Schmitt Trigger
5.11.8
Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
5.11.9
Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
5.11.10
Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
5.11.11
Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
5.11.12
Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
5.11.13
Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
5.11.14
Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
5.12
Device Descriptor (TLV)
5.13
Identification
5.13.1
Revision Identification
5.13.2
Device Identification
5.13.3
JTAG Identification
6
Applications, Implementation, and Layout
6.1
Software Best Practices for Radiation Effects Mitigation
6.2
Device Connection and Layout Fundamentals
6.2.1
Power Supply Decoupling and Bulk Capacitors
6.2.2
External Oscillator
6.2.3
JTAG
6.2.4
Reset
6.2.5
Unused Pins
6.2.6
General Layout Recommendations
6.2.7
Do's and Don'ts
6.3
Peripheral- and Interface-Specific Design Information
6.3.1
ADC12_B Peripheral
6.3.1.1
Partial Schematic
6.3.1.2
Design Requirements
6.3.1.3
Detailed Design Procedure
6.3.1.4
Layout Guidelines
7
デバイスおよびドキュメントのサポート
7.1
使い始めと次の手順
7.2
ツールとソフトウェア
7.3
ドキュメントのサポート
7.4
放射線情報
7.5
関連リンク
7.6
Community Resources
7.7
商標
7.8
静電気放電に関する注意事項
7.9
Export Control Notice
7.10
Glossary
8
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PHP|48
MPQF051B
RGZ|48
MPQF123F
サーマルパッド・メカニカル・データ
PHP|48
PPTD117D
RGZ|48
QFND014T
発注情報
jajsea9a_oa
jajsea9a_pm
6.3.1
ADC12_B Peripheral