JAJSEA9A December   2017  – March 2018 MSP430FR5969-SP

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Signal Descriptions
      1.      Signal Descriptions
    3. 3.3 Pin Multiplexing
    4. 3.4 Connection of Unused Pins
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 4.5  Typical Characteristics – Active Mode Supply Currents
    6. 4.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 4.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 4.8  Low-Power Mode (LPM3.5, LPM4.5) Supply Currents (Into VCC) Excluding External Current
    9. 4.9  Typical Characteristics, Current Consumption per Module
    10. 4.10 Thermal Resistance Characteristics
    11. 4.11 Timing and Switching Characteristics
      1. 4.11.1  Power Supply Sequencing
        1. Table 4-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 4-2 SVS
      2. 4.11.2  Reset Timing
        1. Table 4-3 Reset Input
      3. 4.11.3  Clock Specifications
        1. Table 4-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 4-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 4-6 DCO
        4. Table 4-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 4-8 Module Oscillator (MODOSC)
      4. 4.11.4  Wake-up Characteristics
        1. Table 4-9   Wake-up Times From Low-Power Modes and Reset
        2. Table 4-10 Typical Wake-up Charge
        3. 4.11.4.1    Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 4.11.5  Digital I/Os
        1. Table 4-11 Digital Inputs
        2. Table 4-12 Digital Outputs
        3. 4.11.5.1    Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        4. Table 4-13 Pin-Oscillator Frequency, Ports Px
        5. 4.11.5.2    Typical Characteristics, Pin-Oscillator Frequency
      6. 4.11.6  Timer_A and Timer_B
        1. Table 4-14 Timer_A
        2. Table 4-15 Timer_B
      7. 4.11.7  eUSCI
        1. Table 4-16 eUSCI (UART Mode) Clock Frequency
        2. Table 4-17 eUSCI (UART Mode)
        3. Table 4-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 4-19 eUSCI (SPI Master Mode)
        5. Table 4-20 eUSCI (SPI Slave Mode)
        6. Table 4-21 eUSCI (I2C Mode)
      8. 4.11.8  ADC
        1. Table 4-22 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 4-23 12-Bit ADC, Timing Parameters
        3. Table 4-24 12-Bit ADC, Linearity Parameters With External Reference
        4. Table 4-25 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
        5. Table 4-26 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
        6. Table 4-27 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
        7. Table 4-28 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
        8. Table 4-29 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
        9. Table 4-30 12-Bit ADC, Temperature Sensor and Built-In V1/2
        10. Table 4-31 12-Bit ADC, External Reference
      9. 4.11.9  Reference
        1. Table 4-32 REF, Built-In Reference
      10. 4.11.10 Comparator
        1. Table 4-33 Comparator_E
      11. 4.11.11 FRAM
        1. Table 4-34 FRAM
    12. 4.12 Emulation and Debug
      1. Table 4-35 JTAG and Spy-Bi-Wire Interface
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  CPU
    3. 5.3  Operating Modes
      1. 5.3.1 Peripherals in Low-Power Modes
        1. 5.3.1.1 Idle Currents of Peripherals in LPM3 and LPM4
    4. 5.4  Interrupt Vector Table and Signatures
    5. 5.5  Memory Organization
    6. 5.6  Bootloader (BSL)
    7. 5.7  JTAG Operation
      1. 5.7.1 JTAG Standard Interface
      2. 5.7.2 Spy-Bi-Wire Interface
    8. 5.8  FRAM
    9. 5.9  Memory Protection Unit Including IP Encapsulation
    10. 5.10 Peripherals
      1. 5.10.1  Digital I/O
      2. 5.10.2  Oscillator and Clock System (CS)
      3. 5.10.3  Power-Management Module (PMM)
      4. 5.10.4  Hardware Multiplier (MPY)
      5. 5.10.5  Real-Time Clock (RTC_B) (Only MSP430FR596x and MSP430FR594x)
      6. 5.10.6  Watchdog Timer (WDT_A)
      7. 5.10.7  System Module (SYS)
      8. 5.10.8  DMA Controller
      9. 5.10.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 5.10.10 TA0, TA1
      11. 5.10.11 TA2, TA3
      12. 5.10.12 TB0
      13. 5.10.13 ADC12_B
      14. 5.10.14 Comparator_E
      15. 5.10.15 CRC16
      16. 5.10.16 AES256 Accelerator
      17. 5.10.17 True Random Seed
      18. 5.10.18 Shared Reference (REF)
      19. 5.10.19 Embedded Emulation
        1. 5.10.19.1 Embedded Emulation Module (EEM)
        2. 5.10.19.2 EnergyTrace++ Technology
      20. 5.10.20 Peripheral File Map
    11. 5.11 Input and Output Diagrams
      1. 5.11.1  Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      2. 5.11.2  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      3. 5.11.3  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      4. 5.11.4  Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      5. 5.11.5  Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      6. 5.11.6  Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      7. 5.11.7  Port P2 (P2.7) Input/Output With Schmitt Trigger
      8. 5.11.8  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      9. 5.11.9  Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
      10. 5.11.10 Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
      11. 5.11.11 Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
      12. 5.11.12 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
      13. 5.11.13 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
      14. 5.11.14 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 5.12 Device Descriptor (TLV)
    13. 5.13 Identification
      1. 5.13.1 Revision Identification
      2. 5.13.2 Device Identification
      3. 5.13.3 JTAG Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Software Best Practices for Radiation Effects Mitigation
    2. 6.2 Device Connection and Layout Fundamentals
      1. 6.2.1 Power Supply Decoupling and Bulk Capacitors
      2. 6.2.2 External Oscillator
      3. 6.2.3 JTAG
      4. 6.2.4 Reset
      5. 6.2.5 Unused Pins
      6. 6.2.6 General Layout Recommendations
      7. 6.2.7 Do's and Don'ts
    3. 6.3 Peripheral- and Interface-Specific Design Information
      1. 6.3.1 ADC12_B Peripheral
        1. 6.3.1.1 Partial Schematic
        2. 6.3.1.2 Design Requirements
        3. 6.3.1.3 Detailed Design Procedure
        4. 6.3.1.4 Layout Guidelines
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1  使い始めと次の手順
    2. 7.2  ツールとソフトウェア
    3. 7.3  ドキュメントのサポート
    4. 7.4  放射線情報
    5. 7.5  関連リンク
    6. 7.6  Community Resources
    7. 7.7  商標
    8. 7.8  静電気放電に関する注意事項
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.4 Active Mode Supply Current Into VCC Excluding External Current

over recommended operating temperature (unless otherwise noted)(1)(2)
PARAMETER EXECUTION MEMORY VCC FREQUENCY (fMCLK = fSMCLK) UNIT
1 MHz
0 wait states
(NWAITSx = 0)		 4 MHz
0 wait states
(NWAITSx = 0)		 8 MHz
0 wait states
(NWAITSx = 0)		 12 MHz
1 wait states
(NWAITSx = 1)		 16 MHz
1 wait states
(NWAITSx = 1)
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
IAM, FRAM_UNI
(Unified memory)(3) 		FRAM 3.0 V 210 640 1220 1475 1845 µA
IAM, FRAM (0%)(4)(5) FRAM
0% cache hit ratio		 3.0 V 370 1280 2510 2080 2650 µA
IAM, FRAM (50%)(4)(5) FRAM
50% cache hit ratio		 3.0 V 240 745 1440 1575 1990 µA
IAM, FRAM (66%)(4)(5) FRAM
66% cache hit ratio		 3.0 V 200 560 1070 1300 1620 µA
IAM, FRAM (75%)(4)(5) FRAM
75% cache hit ratio		 3.0 V 170 255 480 890 1085 1155 1310 1420 1620 µA
IAM, FRAM (100%)(4)(5) FRAM
100% cache hit ratio		 3.0 V 110 235 420 640 730 µA
IAM, RAM(6) RAM 3.0 V 130 320 585 890 1070 µA
IAM, RAM only(7)(5) RAM 3.0 V 100 180 290 555 860 1040 1300 µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Characterized with program executing typical data processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO= 24 MHz and fMCLK = fSMCLK = fDCO/2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency (fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait states or the cache hit ratio.
The following equation can be used to compute fMCLK,eff:
fMCLK,eff = fMCLK / [wait states × (1 – cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio, fMCKL,eff = fMCLK / [1 × (1 – 0.75) + 1] = fMCLK / 1.25.
(3) Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.
(4) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are FRAM accesses.
(5) See Figure 4-2 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best linear fit using the typical data from Section 4.4.
(6) Program and data reside entirely in RAM. All execution is from RAM.
(7) Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.