JAJSEA9A December 2017 – March 2018 MSP430FR5969-SP
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|
feUSCI | eUSCI input clock frequency | Internal: SMCLK or ACLK,
External: UCLK, Duty cycle = 50% ±10% |
16 | MHz | |
fBITCLK | BITCLK clock frequency
(equals baud rate in MBaud) |
4 | MHz |
Table 4-17 lists the deglitch times of the eUSCI in UART mode.