JAJSEA9A December   2017  – March 2018 MSP430FR5969-SP

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Signal Descriptions
      1.      Signal Descriptions
    3. 3.3 Pin Multiplexing
    4. 3.4 Connection of Unused Pins
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 4.5  Typical Characteristics – Active Mode Supply Currents
    6. 4.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 4.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 4.8  Low-Power Mode (LPM3.5, LPM4.5) Supply Currents (Into VCC) Excluding External Current
    9. 4.9  Typical Characteristics, Current Consumption per Module
    10. 4.10 Thermal Resistance Characteristics
    11. 4.11 Timing and Switching Characteristics
      1. 4.11.1  Power Supply Sequencing
        1. Table 4-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 4-2 SVS
      2. 4.11.2  Reset Timing
        1. Table 4-3 Reset Input
      3. 4.11.3  Clock Specifications
        1. Table 4-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 4-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 4-6 DCO
        4. Table 4-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 4-8 Module Oscillator (MODOSC)
      4. 4.11.4  Wake-up Characteristics
        1. Table 4-9   Wake-up Times From Low-Power Modes and Reset
        2. Table 4-10 Typical Wake-up Charge
        3. 4.11.4.1    Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 4.11.5  Digital I/Os
        1. Table 4-11 Digital Inputs
        2. Table 4-12 Digital Outputs
        3. 4.11.5.1    Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        4. Table 4-13 Pin-Oscillator Frequency, Ports Px
        5. 4.11.5.2    Typical Characteristics, Pin-Oscillator Frequency
      6. 4.11.6  Timer_A and Timer_B
        1. Table 4-14 Timer_A
        2. Table 4-15 Timer_B
      7. 4.11.7  eUSCI
        1. Table 4-16 eUSCI (UART Mode) Clock Frequency
        2. Table 4-17 eUSCI (UART Mode)
        3. Table 4-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 4-19 eUSCI (SPI Master Mode)
        5. Table 4-20 eUSCI (SPI Slave Mode)
        6. Table 4-21 eUSCI (I2C Mode)
      8. 4.11.8  ADC
        1. Table 4-22 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 4-23 12-Bit ADC, Timing Parameters
        3. Table 4-24 12-Bit ADC, Linearity Parameters With External Reference
        4. Table 4-25 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
        5. Table 4-26 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
        6. Table 4-27 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
        7. Table 4-28 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
        8. Table 4-29 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
        9. Table 4-30 12-Bit ADC, Temperature Sensor and Built-In V1/2
        10. Table 4-31 12-Bit ADC, External Reference
      9. 4.11.9  Reference
        1. Table 4-32 REF, Built-In Reference
      10. 4.11.10 Comparator
        1. Table 4-33 Comparator_E
      11. 4.11.11 FRAM
        1. Table 4-34 FRAM
    12. 4.12 Emulation and Debug
      1. Table 4-35 JTAG and Spy-Bi-Wire Interface
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  CPU
    3. 5.3  Operating Modes
      1. 5.3.1 Peripherals in Low-Power Modes
        1. 5.3.1.1 Idle Currents of Peripherals in LPM3 and LPM4
    4. 5.4  Interrupt Vector Table and Signatures
    5. 5.5  Memory Organization
    6. 5.6  Bootloader (BSL)
    7. 5.7  JTAG Operation
      1. 5.7.1 JTAG Standard Interface
      2. 5.7.2 Spy-Bi-Wire Interface
    8. 5.8  FRAM
    9. 5.9  Memory Protection Unit Including IP Encapsulation
    10. 5.10 Peripherals
      1. 5.10.1  Digital I/O
      2. 5.10.2  Oscillator and Clock System (CS)
      3. 5.10.3  Power-Management Module (PMM)
      4. 5.10.4  Hardware Multiplier (MPY)
      5. 5.10.5  Real-Time Clock (RTC_B) (Only MSP430FR596x and MSP430FR594x)
      6. 5.10.6  Watchdog Timer (WDT_A)
      7. 5.10.7  System Module (SYS)
      8. 5.10.8  DMA Controller
      9. 5.10.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 5.10.10 TA0, TA1
      11. 5.10.11 TA2, TA3
      12. 5.10.12 TB0
      13. 5.10.13 ADC12_B
      14. 5.10.14 Comparator_E
      15. 5.10.15 CRC16
      16. 5.10.16 AES256 Accelerator
      17. 5.10.17 True Random Seed
      18. 5.10.18 Shared Reference (REF)
      19. 5.10.19 Embedded Emulation
        1. 5.10.19.1 Embedded Emulation Module (EEM)
        2. 5.10.19.2 EnergyTrace++ Technology
      20. 5.10.20 Peripheral File Map
    11. 5.11 Input and Output Diagrams
      1. 5.11.1  Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      2. 5.11.2  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      3. 5.11.3  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      4. 5.11.4  Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      5. 5.11.5  Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      6. 5.11.6  Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      7. 5.11.7  Port P2 (P2.7) Input/Output With Schmitt Trigger
      8. 5.11.8  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      9. 5.11.9  Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
      10. 5.11.10 Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
      11. 5.11.11 Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
      12. 5.11.12 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
      13. 5.11.13 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
      14. 5.11.14 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 5.12 Device Descriptor (TLV)
    13. 5.13 Identification
      1. 5.13.1 Revision Identification
      2. 5.13.2 Device Identification
      3. 5.13.3 JTAG Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Software Best Practices for Radiation Effects Mitigation
    2. 6.2 Device Connection and Layout Fundamentals
      1. 6.2.1 Power Supply Decoupling and Bulk Capacitors
      2. 6.2.2 External Oscillator
      3. 6.2.3 JTAG
      4. 6.2.4 Reset
      5. 6.2.5 Unused Pins
      6. 6.2.6 General Layout Recommendations
      7. 6.2.7 Do's and Don'ts
    3. 6.3 Peripheral- and Interface-Specific Design Information
      1. 6.3.1 ADC12_B Peripheral
        1. 6.3.1.1 Partial Schematic
        2. 6.3.1.2 Design Requirements
        3. 6.3.1.3 Detailed Design Procedure
        4. 6.3.1.4 Layout Guidelines
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1  使い始めと次の手順
    2. 7.2  ツールとソフトウェア
    3. 7.3  ドキュメントのサポート
    4. 7.4  放射線情報
    5. 7.5  関連リンク
    6. 7.6  Community Resources
    7. 7.7  商標
    8. 7.8  静電気放電に関する注意事項
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

3.2 Signal Descriptions

describes the signals for all device variants and package options.

Signal Descriptions

TERMINAL I/O(2) DESCRIPTION
NAME NO.(1)
RGZ and PHP
P1.0/TA0.1/DMAE0/ RTCCLK/A0/C0/VREF-/ VeREF- 1 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA0 CCR1 capture: CCI1A input, compare: Out1
External DMA trigger
RTC clock calibration output (not available on MSP430FR5x5x devices)
Analog input A0 for ADC
Comparator input C0
Output of negative reference voltage
Input for an external negative reference voltage to the ADC
P1.1/TA0.2/TA1CLK/ COUT/A1/C1/VREF+/ VeREF+ 2 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA0 CCR2 capture: CCI2A input, compare: Out2
TA1 input clock
Comparator output
Analog input A1 for ADC
Comparator input C1
Output of positive reference voltage
Input for an external positive reference voltage to the ADC
P1.2/TA1.1/TA0CLK/ COUT/A2/C2 3 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA1 CCR1 capture: CCI1A input, compare: Out1
TA0 input clock
Comparator output
Analog input A2 for ADC
Comparator input C2
P3.0/A12/C12 4 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
Analog input A12 for ADC
Comparator input C12
P3.1/A13/C13 5 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
Analog input A13 for ADC
Comparator input C13
P3.2/A14/C14 6 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
Analog input A14 for ADC
Comparator input C14
P3.3/A15/C15 7 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
Analog input A15 for ADC
Comparator input C15
P4.7 8 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.3/TA1.2/UCB0STE/ A3/C3 9 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA1 CCR2 capture: CCI2A input, compare: Out2
Slave transmit enable – eUSCI_B0 SPI mode
Analog input A3 for ADC
Comparator input C3
P1.4/TB0.1/UCA0STE/ A4/C4 10 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR1 capture: CCI1A input, compare: Out1
Slave transmit enable – eUSCI_A0 SPI mode
Analog input A4 for ADC
Comparator input C4
P1.5/TB0.2/UCA0CLK/ A5/C5 11 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR2 capture: CCI2A input, compare: Out2
Clock signal input – eUSCI_A0 SPI slave mode,
Clock signal output – eUSCI_A0 SPI master mode
Analog input A5 for ADC
Comparator input C5
PJ.0/TDO/TB0OUTH/ SMCLK/SRSCG1/C6 12 I/O General-purpose digital I/O
Test data output port
Switch all PWM outputs high impedance input – TB0
SMCLK output
Low-Power Debug: CPU Status Register Bit SCG1
Comparator input C6
PJ.1/TDI/TCLK/MCLK/ SRSCG0/C7 13 I/O General-purpose digital I/O
Test data input or test clock input
MCLK output
Low-Power Debug: CPU Status Register Bit SCG0
Comparator input C7
PJ.2/TMS/ACLK/ SROSCOFF/C8 14 I/O General-purpose digital I/O
Test mode select
ACLK output
Low-Power Debug: CPU Status Register Bit OSCOFF
Comparator input C8
PJ.3/TCK/ SRCPUOFF/C9 15 I/O General-purpose digital I/O
Test clock
Low-Power Debug: CPU Status Register Bit CPUOFF
Comparator input C9
P4.0/A8 16 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
Analog input A8 for ADC
P4.1/A9 17 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
Analog input A9 for ADC
P4.2/A10 18 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
Analog input A10 for ADC
P4.3/A11 19 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
Analog input A11 for ADC
P2.5/TB0.0/UCA1TXD/ UCA1SIMO 20 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR0 capture: CCI0B input, compare: Out0
Transmit data – eUSCI_A1 UART mode
Slave in, master out – eUSCI_A1 SPI mode
P2.6/TB0.1/UCA1RXD/ UCA1SOMI 21 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR1 compare: Out1
Receive data – eUSCI_A1 UART mode
Slave out, master in – eUSCI_A1 SPI mode
TEST/SBWTCK 22 I Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
RST/NMI/SBWTDIO 23 I/O Reset input active low
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
P2.0/TB0.6/UCA0TXD/ UCA0SIMO/TB0CLK/ ACLK 24 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR6 capture: CCI6B input, compare: Out6
Transmit data – eUSCI_A0 UART mode
BSL Transmit (UART BSL)
Slave in, master out – eUSCI_A0 SPI mode
TB0 clock input
ACLK output
P2.1/TB0.0/UCA0RXD/ UCA0SOMI/TB0.0 25 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR0 capture: CCI0A input, compare: Out0
Receive data – eUSCI_A0 UART mode
BSL receive (UART BSL)
Slave out, master in – eUSCI_A0 SPI mode
TB0 CCR0 capture: CCI0A input, compare: Out0
P2.2/TB0.2/UCB0CLK 26 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR2 compare: Out2
Clock signal input – eUSCI_B0 SPI slave mode
Clock signal output – eUSCI_B0 SPI master mode
P3.4/TB0.3/SMCLK 27 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR3 capture: CCI3A input, compare: Out3
SMCLK output
P3.5/TB0.4/COUT 28 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR4 capture: CCI4A input, compare: Out4
Comparator output
P3.6/TB0.5 29 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR5 capture: CCI5A input, compare: Out5
P3.7/TB0.6 30 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR6 capture: CCI6A input, compare: Out6
P1.6/TB0.3/UCB0SIMO/ UCB0SDA/TA0.0 31 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR3 capture: CCI3B input, compare: Out3
Slave in, master out – eUSCI_B0 SPI mode
I2C data – eUSCI_B0 I2C mode
BSL Data (I2C BSL)
TA0 CCR0 capture: CCI0A input, compare: Out0
P1.7/TB0.4/UCB0SOMI/ UCB0SCL/TA1.0 32 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR4 capture: CCI4B input, compare: Out4
Slave out, master in – eUSCI_B0 SPI mode
I2C clock – eUSCI_B0 I2C mode
BSL clock (I2C BSL)
TA1 CCR0 capture: CCI0A input, compare: Out0
P4.4/TB0.5 33 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0CCR5 capture: CCI5B input, compare: Out5
P4.5 34 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.6 35 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
DVSS 36 Digital ground supply
DVCC 37 Digital power supply
P2.7 38 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.3/TA0.0/UCA1STE/ A6/C10 39 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA0 CCR0 capture: CCI0B input, compare: Out0
Slave transmit enable – eUSCI_A1 SPI mode
Analog input A6 for ADC
Comparator input C10
P2.4/TA1.0/UCA1CLK/ A7/C11 40 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA1 CCR0 capture: CCI0B input, compare: Out0
Clock signal input – eUSCI_A1 SPI slave mode
Clock signal output – eUSCI_A1 SPI master mode
Analog input A7 for ADC
Comparator input C11
AVSS 41 Analog ground supply
PJ.6/HFXIN 42 I/O General-purpose digital I/O
Input for high-frequency crystal oscillator HFXT (in RHA and DA packages: MSP430FR595x devices only)
PJ.7/HFXOUT 43 I/O General-purpose digital I/O
Output for high-frequency crystal oscillator HFXT (in RHA and DA packages: MSP430FR595x devices only)
AVSS 44 Analog ground supply
PJ.4/LFXIN 45 I/O General-purpose digital I/O
Input for low-frequency crystal oscillator LFXT (in RHA and DA packages: MSP430FR594x devices only)
PJ.5/LFXOUT 46 I/O General-purpose digital I/O
Output of low-frequency crystal oscillator LFXT (in RHA and DA packages: MSP430FR594x devices only)
AVSS 47 Analog ground supply
AVCC 48 Analog power supply
QFN Pad Pad QFN package exposed thermal pad. TI recommends connection to VSS.
(1) N/A = not available
(2) I = input, O = output