JAJSG26C March   2016  – August 2018 MSP430FR5962 , MSP430FR5964 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Types
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics, Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 5.10 Typical Characteristics, Current Consumption per Module
    11. 5.11 Thermal Packaging Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.12.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.12.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.12.4  Wake-up Characteristics
        1. Table 5-9  Wake-up Times From Low-Power Modes and Reset
        2. 5.12.4.1   Typical Characteristics, Average LPM Currents vs Wake-up Frequency
        3. Table 5-10 Typical Wake-up Charge
      5. 5.12.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.12.5.1   Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        4. Table 5-13 Pin-Oscillator Frequency, Ports Px
        5. 5.12.5.2   Typical Characteristics, Pin-Oscillator Frequency
      6. 5.12.6  LEA (Low-Energy Accelerator) (MSP430FR599x Only)
        1. Table 5-14 Low Energy Accelerator Performance
      7. 5.12.7  Timer_A and Timer_B
        1. Table 5-15 Timer_A
        2. Table 5-16 Timer_B
      8. 5.12.8  eUSCI
        1. Table 5-17 eUSCI (UART Mode) Clock Frequency
        2. Table 5-18 eUSCI (UART Mode)
        3. Table 5-19 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-20 eUSCI (SPI Master Mode)
        5. Table 5-21 eUSCI (SPI Slave Mode)
        6. Table 5-22 eUSCI (I2C Mode)
      9. 5.12.9  ADC12_B
        1. Table 5-23 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-24 12-Bit ADC, Timing Parameters
        3. Table 5-25 12-Bit ADC, Linearity Parameters
        4. Table 5-26 12-Bit ADC, Dynamic Performance With External Reference
        5. Table 5-27 12-Bit ADC, Dynamic Performance With Internal Reference
        6. Table 5-28 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. Table 5-29 12-Bit ADC, External Reference
      10. 5.12.10 Reference
        1. Table 5-30 REF, Built-In Reference
      11. 5.12.11 Comparator
        1. Table 5-31 Comparator_E
      12. 5.12.12 FRAM
        1. Table 5-32 FRAM
      13. 5.12.13 Emulation and Debug
        1. Table 5-33 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Low-Energy Accelerator (LEA) for Signal Processing (MSP430FR599x Only)
    4. 6.4  Operating Modes
      1. 6.4.1 Peripherals in Low-Power Modes
      2. 6.4.2 Idle Currents of Peripherals in LPM3 and LPM4
    5. 6.5  Interrupt Vector Table and Signatures
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  FRAM Controller A (FRCTL_A)
    9. 6.9  RAM
    10. 6.10 Tiny RAM
    11. 6.11 Memory Protection Unit (MPU) Including IP Encapsulation
    12. 6.12 Peripherals
      1. 6.12.1  Digital I/O
      2. 6.12.2  Oscillator and Clock System (CS)
      3. 6.12.3  Power-Management Module (PMM)
      4. 6.12.4  Hardware Multiplier (MPY)
      5. 6.12.5  Real-Time Clock (RTC_C)
      6. 6.12.6  Watchdog Timer (WDT_A)
      7. 6.12.7  System Module (SYS)
      8. 6.12.8  DMA Controller
      9. 6.12.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.12.10 TA0, TA1, and TA4
      11. 6.12.11 TA2 and TA3
      12. 6.12.12 TB0
      13. 6.12.13 ADC12_B
      14. 6.12.14 Comparator_E
      15. 6.12.15 CRC16
      16. 6.12.16 CRC32
      17. 6.12.17 AES256 Accelerator
      18. 6.12.18 True Random Seed
      19. 6.12.19 Shared Reference (REF)
      20. 6.12.20 Embedded Emulation
        1. 6.12.20.1 Embedded Emulation Module (EEM) (S Version)
        2. 6.12.20.2 EnergyTrace++ Technology
    13. 6.13 Input/Output Diagrams
      1. 6.13.1  Capacitive Touch Functionality on Ports P1 to P8, and PJ
      2. 6.13.2  Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      3. 6.13.3  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      4. 6.13.4  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      5. 6.13.5  Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      6. 6.13.6  Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      7. 6.13.7  Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      8. 6.13.8  Port P2 (P2.7) Input/Output With Schmitt Trigger
      9. 6.13.9  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      10. 6.13.10 Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
      11. 6.13.11 Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
      12. 6.13.12 Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
      13. 6.13.13 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      14. 6.13.14 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      15. 6.13.15 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      16. 6.13.16 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      17. 6.13.17 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
      18. 6.13.18 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      19. 6.13.19 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
      20. 6.13.20 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    14. 6.14 Device Descriptors (TLV)
    15. 6.15 Memory Map
      1. 6.15.1 Peripheral File Map
    16. 6.16 Identification
      1. 6.16.1 Revision Identification
      2. 6.16.2 Device Identification
      3. 6.16.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  使い始めと次の手順
    2. 8.2  デバイスの項目表記
    3. 8.3  ツールとソフトウェア
    4. 8.4  ドキュメントのサポート
    5. 8.5  関連リンク
    6. 8.6  Community Resources
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Pin Attributes

Table 4-1 summarizes the attributes of the pins.

Table 4-1 Pin Attributes

PIN NUMBER(1) SIGNAL NAME(1)(4) SIGNAL TYPE(2) BUFFER TYPE(3) POWER SOURCE(5) RESET STATE AFTER BOR(6)
PN PM RGZ ZVW
1 1 1 A10 P1.0 I/O LVCMOS DVCC OFF
TA0.1 I/O LVCMOS DVCC
DMAE0 I LVCMOS DVCC
RTCCLK O LVCMOS DVCC
A0 I Analog DVCC
C0 I Analog DVCC
VREF- O Analog DVCC
VeREF- I Analog DVCC
2 2 2 A9 P1.1 I/O LVCMOS DVCC OFF
TA0.2 I/O LVCMOS DVCC
TA1CLK I LVCMOS DVCC
COUT O LVCMOS DVCC
A1 I Analog DVCC
C1 I Analog DVCC
VREF+ O Analog DVCC
VeREF+ I Analog DVCC
3 3 3 B9 P1.2 I/O LVCMOS DVCC OFF
TA1.1 I/O LVCMOS DVCC
TA0CLK I LVCMOS DVCC
COUT O LVCMOS DVCC
A2 I Analog DVCC
C2 I Analog DVCC
4 4 4 A8 P3.0 I/O LVCMOS DVCC OFF
A12 I Analog DVCC
C12 I Analog DVCC
5 5 5 B8 P3.1 I/O LVCMOS DVCC
A13 I Analog DVCC
C13 I Analog DVCC
6 6 6 B7 P3.2 I/O LVCMOS DVCC OFF
A14 I Analog DVCC
C14 I Analog DVCC
7 7 7 A7 P3.3 I/O LVCMOS DVCC OFF
A15 I Analog DVCC
C15 I Analog DVCC
8 D8 P6.0 I/O LVCMOS DVCC OFF
UCA3TXD O LVCMOS DVCC
UCA3SIMO I/O LVCMOS DVCC
9 D7 P6.1 I/O LVCMOS DVCC OFF
UCA3RXD I LVCMOS DVCC
UCA3SOMI I/O LVCMOS DVCC
10 A6 P6.2 I/O LVCMOS DVCC OFF
UCA3CLK I/O LVCMOS DVCC
11 B6 P6.3 I/O LVCMOS DVCC OFF
UCA3STE I/O LVCMOS DVCC
12 8 8 D6 P4.7 I/O LVCMOS DVCC OFF
13 9 A5 P7.0 I/O LVCMOS DVCC OFF
UCB2SIMO I/O LVCMOS DVCC
UCB2SDA I/O LVCMOS DVCC
14 10 B5 P7.1 I/O LVCMOS DVCC OFF
UCB2SOMI I/O LVCMOS DVCC
UCB2SCL I/O LVCMOS DVCC
15 11 D5 P8.0 I/O LVCMOS DVCC OFF
16 12 9 A4 P1.3 I/O LVCMOS DVCC OFF
TA1.2 I/O LVCMOS DVCC
UCB0STE I/O LVCMOS DVCC
A3 I Analog DVCC
C3 I Analog DVCC
17 13 10 B3 P1.4 I/O LVCMOS DVCC OFF
TB0.1 I/O LVCMOS DVCC
UCA0STE I/O LVCMOS DVCC
A4 I Analog DVCC
C4 I Analog DVCC
18 14 11 B4 P1.5 I/O LVCMOS DVCC OFF
TB0.2 I/O LVCMOS DVCC
UCA0CLK I/O LVCMOS DVCC
A5 I Analog DVCC
C5 I Analog DVCC
19 15 A2 DVSS2 P Power N/A
20 16 A3 DVCC2 P Power N/A
21 17 12 B1 PJ.0 I/O LVCMOS DVCC OFF
TDO O LVCMOS DVCC
TB0OUTH I LVCMOS DVCC
SMCLK O LVCMOS DVCC
SRSCG1 O LVCMOS DVCC
C6 I Analog DVCC
22 18 13 C1 PJ.1 I/O LVCMOS DVCC OFF
TDI I LVCMOS DVCC
TCLK I LVCMOS DVCC
MCLK O LVCMOS DVCC
SRSCG0 O LVCMOS DVCC
C7 I Analog DVCC
23 19 14 C2 PJ.2 I/O LVCMOS DVCC OFF
TMS I LVCMOS DVCC
ACLK O LVCMOS DVCC
SROSCOFF O LVCMOS DVCC
C8 I Analog DVCC
24 20 15 D2 PJ.3 I/O LVCMOS DVCC OFF
TCK I LVCMOS DVCC
SRCPUOFF O LVCMOS DVCC
C9 I Analog DVCC
25 21 D1 P7.2 I/O LVCMOS DVCC OFF
UCB2CLK I/O LVCMOS DVCC
26 22 D4 P7.3 I/O LVCMOS DVCC OFF
UCB2STE I/O LVCMOS DVCC
TA4.1 I/O LVCMOS DVCC
27 23 E1 P7.4 I/O LVCMOS DVCC OFF
TA4.0 I/O LVCMOS DVCC
A16 I Analog DVCC
28 E2 P7.5 I/O LVCMOS DVCC OFF
A17 I Analog DVCC
29 E4 P7.6 I/O LVCMOS DVCC OFF
A18 I Analog DVCC
30 F2 P7.7 I/O LVCMOS DVCC OFF
A19 I Analog DVCC
31 24 16 F1 P4.0 I/O LVCMOS DVCC OFF
A8 I Analog DVCC
32 25 17 F4 P4.1 I/O LVCMOS DVCC OFF
A9 I Analog DVCC
33 26 18 G1 P4.2 I/O LVCMOS DVCC OFF
A10 I Analog DVCC
34 27 19 G2 P4.3 I/O LVCMOS DVCC OFF
A11 I Analog DVCC
35 28 20 G4 P2.5 I/O LVCMOS DVCC OFF
TB0.0 I/O LVCMOS DVCC
UCA1TXD O LVCMOS DVCC
UCA1SIMO I/O LVCMOS DVCC
36 29 21 H1 P2.6 I/O LVCMOS DVCC OFF
TB0.1 O LVCMOS DVCC
UCA1RXD I LVCMOS DVCC
UCA1SOMI I/O LVCMOS DVCC
37 30 22 H2 TEST I LVCMOS DVCC OFF
SBWTCK I LVCMOS DVCC
38 31 23 J2 RST I LVCMOS DVCC OFF
NMI I LVCMOS DVCC
SBWTDIO I/O LVCMOS DVCC
39 J1 DVSS3 P Power N/A
40 K1 DVCC3 P Power N/A
41 32 24 L2 P2.0 I/O LVCMOS DVCC OFF
TB0.6 I/O LVCMOS DVCC
UCA0TXD O LVCMOS DVCC
BSLTX O LVCMOS DVCC
UCA0SIMO I/O LVCMOS DVCC
TB0CLK I LVCMOS DVCC
ACLK O LVCMOS DVCC
42 33 25 L3 P2.1 I/O LVCMOS DVCC OFF
TB0.0 I/O LVCMOS DVCC
UCA0RXD I LVCMOS DVCC
BSLRX I LVCMOS DVCC
UCA0SOMI I/O LVCMOS DVCC
43 34 26 K3 P2.2 I/O LVCMOS DVCC OFF
TB0.2 O LVCMOS DVCC
UCB0CLK I/O LVCMOS DVCC
44 L4 P8.1 I/O LVCMOS DVCC OFF
45 K4 P8.2 I/O LVCMOS DVCC OFF
46 H4 P8.3 I/O LVCMOS DVCC OFF
47 35 27 K5 P3.4 I/O LVCMOS DVCC OFF
TB0.3 I/O LVCMOS DVCC
SMCLK O LVCMOS DVCC
48 36 28 L5 P3.5 I/O LVCMOS DVCC OFF
TB0.4 I/O LVCMOS DVCC
COUT O LVCMOS DVCC
49 37 29 H5 P3.6 I/O LVCMOS DVCC OFF
TB0.5 I/O LVCMOS DVCC
50 38 30 H6 P3.7 I/O LVCMOS DVCC OFF
TB0.6 I/O LVCMOS DVCC
51 39 31 L6 P1.6 I/O LVCMOS DVCC OFF
TB0.3 I/O LVCMOS DVCC
UCB0SIMO I/O LVCMOS DVCC
UCB0SDA I/O LVCMOS DVCC
BSLSDA I/O LVCMOS DVCC
TA0.0 I/O LVCMOS DVCC
52 40 32 K6 P1.7 I/O LVCMOS DVCC OFF
TB0.4 I/O LVCMOS DVCC
UCB0SOMI I/O LVCMOS DVCC
UCB0SCL I/O LVCMOS DVCC
BSLSCL I/O LVCMOS DVCC
TA1.0 I/O LVCMOS DVCC
53 41 L7 P5.0 I/O LVCMOS DVCC OFF
UCB1SIMO I/O LVCMOS DVCC
UCB1SDA I/O LVCMOS DVCC
54 42 K7 P5.1 I/O LVCMOS DVCC OFF
UCB1SOMI I/O LVCMOS DVCC
UCB1SCL I/O LVCMOS DVCC
55 43 K8 P5.2 I/O LVCMOS DVCC OFF
UCB1CLK I/O LVCMOS DVCC
TA4CLK I LVCMOS DVCC
56 44 L8 P5.3 I/O LVCMOS DVCC OFF
UCB1STE I/O LVCMOS DVCC
57 45 33 H7 P4.4 I/O LVCMOS DVCC OFF
TB0.5 I/O LVCMOS DVCC
58 46 34 H8 P4.5 I/O LVCMOS DVCC OFF
59 47 35 K9 P4.6 I/O LVCMOS DVCC OFF
60 48 36 L9 DVSS1 P Power N/A
61 49 37 L10 DVCC1 P Power N/A
62 50 38 F11 P2.7 I/O LVCMOS DVCC OFF
63 51 39 J11 P2.3 I/O LVCMOS DVCC OFF
TA0.0 I/O LVCMOS DVCC
UCA1STE I/O LVCMOS DVCC
A6 I Analog DVCC
C10 I Analog DVCC
64 52 40 K11 P2.4 I/O LVCMOS DVCC OFF
TA1.0 I/O LVCMOS DVCC
UCA1CLK I/O LVCMOS DVCC
A7 I Analog DVCC
C11 I Analog DVCC
65 53 J10 P5.4 I/O LVCMOS DVCC OFF
UCA2TXD O LVCMOS DVCC
UCA2SIMO I/O LVCMOS DVCC
TB0OUTH I LVCMOS DVCC
66 54 H10 P5.5 I/O LVCMOS DVCC OFF
UCA2RXD I LVCMOS DVCC
UCA2SOMI I/O LVCMOS DVCC
ACLK O LVCMOS DVCC
67 55 G10 P5.6 I/O LVCMOS DVCC OFF
UCA2CLK I/O LVCMOS DVCC
TA4.0 I/O LVCMOS DVCC
SMCLK O LVCMOS DVCC
68 56 G8 P5.7 I/O LVCMOS DVCC OFF
UCA2STE I/O LVCMOS DVCC
TA4.1 I/O LVCMOS DVCC
MCLK O LVCMOS DVCC
69 F8 P6.4 I/O LVCMOS DVCC OFF
UCB3SIMO I/O LVCMOS DVCC
UCB3SDA I/O LVCMOS DVCC
70 F10 P6.5 I/O LVCMOS DVCC OFF
UCB3SOMI I/O LVCMOS DVCC
UCB3SCL I/O LVCMOS DVCC
71 E8 P6.6 I/O LVCMOS DVCC OFF
UCB3CLK I/O LVCMOS DVCC
72 C10 P6.7 I/O LVCMOS DVCC OFF
UCB3STE I/O LVCMOS DVCC
73 57 41 E10 AVSS3 P Power N/A
74 58 42 H11 PJ.6 I/O LVCMOS DVCC
HFXIN I Analog DVCC
75 59 43 G11 PJ.7 I/O LVCMOS DVCC OFF
HFXOUT O Analog DVCC
76 60 44 D10 AVSS2 P Power N/A
77 61 45 E11 PJ.4 I/O LVCMOS DVCC OFF
LFXIN I Analog DVCC
78 62 46 D11 PJ.5 I/O LVCMOS DVCC OFF
LFXOUT O Analog DVCC
79 63 47 C11 AVSS1 P Power N/A
80 64 48 B11 AVCC1 P Power N/A
A1 DGND P Power N/A
A11 AGND P Power N/A
B10 AGND P Power N/A
K2 DGND P Power N/A
K10 DGND P Power N/A
L1 DGND P Power N/A
L11 DGND P Power N/A
Pad QFN Pad P Power N/A
The signal that is listed first for each pin is the reset default pin name.
Signal Types: I = Input, O = Output, I/O = Input or Output.
Buffer Types: LVCMOS, Analog, or Power (see Table 4-3 for details)
To determine the pin mux encodings for each pin, see Section 6.13.
The power source shown in this table is the I/O power source, which may differ from the module power source.
Reset States:
OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled
N/A = Not applicable