SLASEV3A March 2020 – December 2020 MSP430FR6005 , MSP430FR6007
PRODUCTION DATA
Table 7-2 describes the signals.
FUNCTION | SIGNAL NAME | PIN NO. | PIN TYPE(1) | DESCRIPTION |
---|---|---|---|---|
PZ | ||||
ADC | A0 | 3 | I | ADC analog input A0 |
A1 | 4 | I | ADC analog input A1 | |
A2 | 12 | I | ADC analog input A2 | |
A3 | 13 | I | ADC analog input A3 | |
A4 | 14 | I | ADC analog input A4 | |
A5 | 15 | I | ADC analog input A5 | |
A6 | 16 | I | ADC analog input A6 | |
A7 | 17 | I | ADC analog input A7 | |
A8 | 18 | I | ADC analog input A8 | |
A9 | 19 | I | ADC analog input A9 | |
A10 | 92 | I | ADC analog input A10 | |
A11 | 93 | I | ADC analog input A11 | |
A12 | 94 | I | ADC analog input A12 | |
A13 | 95 | I | ADC analog input A13 | |
A14 | 1 | I | ADC analog input A14 | |
A15 | 2 | I | ADC analog input A15 | |
VREF+ | 4 | O | Output of positive reference voltage | |
VREF- | 3 | O | Output of negative reference voltage | |
VeREF+ | 4 | I | Input for an external positive reference voltage to the ADC | |
VeREF- | 3 | I | Input for an external negative reference voltage to the ADC | |
Clock | ACLK | 22, 43, 67 | O | ACLK output |
HFXIN | 9 | I | Input for high-frequency crystal oscillator HFXT | |
HFXOUT | 10 | O | Output for high-frequency crystal oscillator HFXT | |
LFXIN | 6 | I | Input for low-frequency crystal oscillator LFXT | |
LFXOUT | 7 | O | Output of low-frequency crystal oscillator LFXT | |
MCLK | 24, 42, 81 | O | MCLK output | |
SMCLK | 23, 41, 68 | O | SMCLK output | |
Comparator | C0 | 3 | I | Comparator input C0 |
C1 | 4 | I | Comparator input C1 | |
C2 | 12 | I | Comparator input C2 | |
C3 | 13 | I | Comparator input C3 | |
C4 | 14 | I | Comparator input C4 | |
C5 | 15 | I | Comparator input C5 | |
C6 | 16 | I | Comparator input C6 | |
C7 | 17 | I | Comparator input C7 | |
C8 | 18 | I | Comparator input C8 | |
C9 | 19 | I | Comparator input C9 | |
C10 | 22 | I | Comparator input C10 | |
C11 | 23 | I | Comparator input C11 | |
C12 | 24 | I | Comparator input C12 | |
C13 | 25 | I | Comparator input C13 | |
C14 | 1 | I | Comparator input C14 | |
C15 | 2 | I | Comparator input C15 | |
COUT | 1, 83, 84 | O | Comparator output | |
DMA | DMAE0 | 22, 79, 83 | I | External DMA trigger |
Debug | SBWTCK | 20 | I | Spy-Bi-Wire input clock |
SBWTDIO | 21 | I/O | Spy-Bi-Wire data input/output | |
SRCPUOFF | 25 | O | Low-power debug: CPU Status register bit CPUOFF | |
SROSCOFF | 24 | O | Low-power debug: CPU Status register bit OSCOFF | |
SRSCG0 | 23 | O | Low-power debug: CPU Status register bit SCG0 | |
SRSCG1 | 22 | O | Low-power debug: CPU Status register bit SCG1 | |
TCK | 25 | I | Test clock | |
TCLK | 23 | I | Test clock input | |
TDI | 23 | I | Test data input | |
TDO | 22 | O | Test data output port | |
TEST | 20 | I | Test mode pin, selects digital I/O on JTAG pins | |
TMS | 24 | I | Test mode select | |
GPIO Port 1 | P1.0 | 3 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 |
P1.1 | 4 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P1.2 | 18 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P1.3 | 19 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P1.4 | 12 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P1.5 | 13 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P1.6 | 14 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P1.7 | 15 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
GPIO Port 2 | P2.0 | 16 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 |
P2.1 | 17 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P2.2 | 1 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P2.3 | 2 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P2.4 | 28 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P2.5 | 29 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P2.6 | 30 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P2.7 | 39 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
GPIO Port 3 | P3.0 | 31 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 |
P3.1 | 32 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P3.2 | 33 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P3.3 | 34 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P3.4 | 35 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P3.5 | 36 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P3.6 | 37 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P3.7 | 38 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
GPIO Port 4 | P4.0 | 44 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 |
P4.1 | 45 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P4.2 | 46 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P4.3 | 47 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P4.4 | 48 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P4.5 | 49 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P4.6 | 50 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P4.7 | 53 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
GPIO Port 5 | P5.0 | 54 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 |
P5.1 | 55 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P5.2 | 56 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P5.3 | 57 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P5.4 | 58 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P5.5 | 59 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P5.6 | 60 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P5.7 | 61 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
GPIO Port 6 | P6.0 | 62 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 |
P6.1 | 71 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P6.2 | 72 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P6.3 | 73 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P6.4 | 63 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P6.5 | 64 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P6.6 | 65 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P6.7 | 66 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
GPIO Port 7 | P7.0 | 67 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 |
P7.1 | 68 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P7.2 | 69 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P7.3 | 70 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P7.4 | 77 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P7.5 | 78 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P7.6 | 83 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P7.7 | 84 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
GPIO Port 8 | P8.0 | 79 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 |
P8.1 | 80 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P8.2 | 81 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P8.3 | 82 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P8.4 | 92 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P8.5 | 93 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P8.6 | 94 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P8.7 | 95 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
GPIO Port 9 | P9.0 | 40 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 |
P9.1 | 41 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P9.2 | 42 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
P9.3 | 43 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
GPIO Port J | PJ.0 | 22 | I/O | General-purpose digital I/O |
PJ.1 | 23 | I/O | General-purpose digital I/O | |
PJ.2 | 24 | I/O | General-purpose digital I/O | |
PJ.3 | 25 | I/O | General-purpose digital I/O | |
PJ.4 | 6 | I/O | General-purpose digital I/O | |
PJ.5 | 7 | I/O | General-purpose digital I/O | |
PJ.6 | 9 | I/O | General-purpose digital I/O | |
PJ.7 | 10 | I/O | General-purpose digital I/O | |
I2C | UCB0SCL | 15 | I/O | I2C clock for eUSCI_B0 I2C mode |
UCB0SDA | 14 | I/O | I2C data for eUSCI_B0 I2C mode | |
UCB1SCL | 94, 60 | I/O | I2C clock for eUSCI_B1 I2C mode | |
UCB1SDA | 93, 59 | I/O | I2C data for eUSCI_B1 I2C mode | |
LCD | COM0 | 63 | O | LCD common output COM0 for LCD backplane |
COM1 | 64 | O | LCD common output COM1 for LCD backplane | |
COM2 | 65 | O | LCD common output COM2 for LCD backplane | |
COM3 | 66 | O | LCD common output COM3 for LCD backplane | |
COM4 | 67 | O | LCD common output COM4 for LCD backplane | |
COM5 | 68 | O | LCD common output COM5 for LCD backplane | |
COM6 | 69 | O | LCD common output COM6 for LCD backplane | |
COM7 | 70 | O | LCD common output COM7 for LCD backplane | |
LCDCAP | 74 | I/O | LCD capacitor connection CAUTION: LCDCAP/R33 must be connected to DVSS if not used. |
|
LCDREF | 72 | I | External reference voltage input for regulated LCD voltage | |
R03 | 71 | I/O | Input/output port of lowest analog LCD voltage (V5) | |
R13 | 72 | I/O | Input/output port of third most positive analog LCD voltage (V3 or V4) | |
R23 | 73 | I/O | Input/output port of second most positive analog LCD voltage (V2) | |
R33 | 74 | I/O | Input/output port of most positive analog LCD voltage (V1) CAUTION: LCDCAP/R33 must be connected to DVSS if not used. |
|
S0 | 62 | O | LCD segment output | |
S1 | 61 | O | LCD segment output | |
S2 | 60 | O | LCD segment output | |
S3 | 59 | O | LCD segment output | |
S4 | 58 | O | LCD segment output | |
S5 | 57 | O | LCD segment output | |
S6 | 56 | O | LCD segment output | |
S7 | 55 | O | LCD segment output | |
S8 | 54 | O | LCD segment output | |
S9 | 53 | O | LCD segment output | |
S10 | 50 | O | LCD segment output | |
S11 | 49 | O | LCD segment output | |
S12 | 48 | O | LCD segment output | |
S13 | 47 | O | LCD segment output | |
S14 | 46 | O | LCD segment output | |
S15 | 45 | O | LCD segment output | |
S16 | 44 | O | LCD segment output | |
S17 | 43 | O | LCD segment output | |
S18 | 42 | O | LCD segment output | |
S19 | 41 | O | LCD segment output | |
S20 | 40 | O | LCD segment output | |
S21 | 39 | O | LCD segment output | |
S22 | 38 | O | LCD segment output | |
S23 | 37 | O | LCD segment output | |
S24 | 36 | O | LCD segment output | |
S25 | 35 | O | LCD segment output | |
S26 | 34 | O | LCD segment output | |
S27 | 33 | O | LCD segment output | |
S28 | 32 | O | LCD segment output | |
LCD (continued) | S29 | 31 | O | LCD segment output |
S30 | 30 | O | LCD segment output | |
S31 | 29 | O | LCD segment output | |
S32 | 28 | O | LCD segment output | |
S33 | 70 | O | LCD segment output | |
S34 | 69 | O | LCD segment output | |
S35 | 68 | O | LCD segment output | |
S36 | 67 | O | LCD segment output | |
S37 | 66 | O | LCD segment output | |
S38 | 65 | O | LCD segment output | |
Power | AVCC1 | 100 | P | Analog power supply |
AVSS1 | 99 | P | Analog ground supply | |
AVSS2 | 5 | P | Analog ground supply | |
AVSS3 | 8 | P | Analog ground supply | |
AVSS4 | 11 | P | Analog ground supply | |
AVSS5 | 96 | P | Analog ground supply | |
DVCC1 | 27 | P | Digital power supply | |
DVCC2 | 52 | P | Digital power supply | |
DVCC3 | 76 | P | Digital power supply | |
DVSS1 | 26 | P | Digital ground supply | |
DVSS2 | 51 | P | Digital ground supply | |
DVSS3 | 75 | P | Digital ground supply | |
PVCC | 88 | P | USS power supply | |
PVSS | 87, 89 | P | USS ground supply | |
RTC | RTCCLK | 25, 44, 82 | O | RTC clock calibration output |
SPI | UCA0CLK | 1, 45 | I/O | Clock signal input for eUSCI_A0 SPI slave mode Clock signal output for eUSCI_A0 SPI master mode |
UCA0SIMO | 16, 47 | I/O | Slave in/master out for eUSCI_A0 SPI mode | |
UCA0SOMI | 17, 48 | I/O | Slave out/master in for eUSCI_A0 SPI mode | |
UCA0STE | 2, 46 | I/O | Slave transmit enable for eUSCI_A0 SPI mode | |
UCA1CLK | 3 | I/O | Clock signal input for eUSCI_A1 SPI slave mode Clock signal output for eUSCI_A1 SPI master mode |
|
UCA1SIMO | 18 | I/O | Slave in/master out for eUSCI_A1 SPI mode | |
UCA1SOMI | 19 | I/O | Slave out/master in for eUSCI_A1 SPI mode | |
UCA1STE | 4 | I/O | Slave transmit enable for eUSCI_A1 SPI mode | |
UCA2CLK | 69, 56 | I/O | Clock signal input for eUSCI_A2 SPI slave mode Clock signal output for eUSCI_A2 SPI master mode |
|
UCA2SIMO | 67, 54 | I/O | Slave in/master out for eUSCI_A2 SPI mode | |
UCA2SOMI | 68, 55 | I/O | Slave out/master in for eUSCI_A2 SPI mode | |
UCA2STE | 70, 57 | I/O | Slave transmit enable for eUSCI_A2 SPI mode | |
UCA3CLK | 80 | I/O | Clock signal input for eUSCI_A3 SPI slave mode Clock signal output for eUSCI_A3 SPI master mode |
|
UCA3SIMO | 82 | I/O | Slave in/master out for eUSCI_A3 SPI mode | |
UCA3SOMI | 81 | I/O | Slave out/master in for eUSCI_A3 SPI mode | |
UCA3STE | 79 | I/O | Slave transmit enable for eUSCI_A3 SPI mode | |
UCB0CLK | 13 | I/O | Clock signal input for eUSCI_B0 SPI slave mode Clock signal output for eUSCI_B0 SPI master mode |
|
UCB0SIMO | 14 | I/O | Slave in/master out for eUSCI_B0 SPI mode | |
UCB0SOMI | 15 | I/O | Slave out/master in for eUSCI_B0 SPI mode | |
UCB0STE | 12 | I/O | Slave transmit enable for eUSCI_B0 SPI mode | |
UCB1CLK | 92, 58 | I/O | Clock signal input for eUSCI_B1 SPI slave mode Clock signal output for eUSCI_B1 SPI master mode |
|
UCB1SIMO | 93, 59 | I/O | Slave in/master out for eUSCI_B1 SPI mode | |
UCB1SOMI | 94, 60 | I/O | Slave out/master in for eUSCI_B1 SPI mode | |
UCB1STE | 95, 61 | I/O | Slave transmit enable for eUSCI_B1 SPI mode | |
System | NMI | 21 | I | Nonmaskable interrupt input |
RST | 21 | I/O | Reset input active low | |
Timer | TA0.0 | 2 | I/O | TA0 CCR0 capture: CCI0A input, compare: Out0 |
TA0.0 | 39 | I/O | TA0 CCR0 capture: CCI0B input, compare: Out0 | |
TA0.1 | 77 | I/O | TA0 CCR1 capture: CCI1A input, compare: Out1 | |
TA0.2 | 84 | I/O | TA0 CCR2 capture: CCI2A input, compare: Out2 | |
TA0CLK | 28, 49, 59 | I | TA0 input clock | |
TA1.0 | 3 | I/O | TA1 CCR0 capture: CCI0A input, compare: Out0 | |
TA1.0 | 40 | I/O | TA1 CCR0 capture: CCI0B input, compare: Out0 | |
TA1.1 | 78 | I/O | TA1 CCR1 capture: CCI1A input, compare: Out1 | |
TA1.2 | 92 | I/O | TA1 CCR2 capture: CCI2A input, compare: Out2 | |
TA1CLK | 28, 49 | I | TA1 input clock | |
TA4.0 | 4 | I/O | TA4 CCR0 capture: CCI0A input, compare: Out0 | |
TA4.0 | 29 | I/O | TA4 CCR0 capture: CCI0B input, compare: Out0 | |
TA4.1 | 30 | I/O | TA4CCR1 capture: CCI1B input, compare: Out1 | |
TA4.1 | 83 | I/O | TA4 CCR1 capture: CCI1A input, compare: Out1 | |
TA4CLK | 23, 50 | I | TA4 input clock | |
TB0.0 | 31 | I/O | TB0 CCR0 capture: CCI0B input, compare: Out0 | |
TB0.0 | 69 | I/O | TB0 CCR0 capture: CCI0A input, compare: Out0 | |
TB0.1 | 32 | I/O | TB0 CCR1 capture: CCI1A input, compare: Out1 | |
TB0.1 | 70 | O | TB0 CCR1 compare: Out1 | |
TB0.2 | 33 | I/O | TB0 CCR2 capture: CCI2A input, compare: Out2 | |
TB0.2 | 79 | O | TB0 CCR2 compare: Out2 | |
TB0.3 | 34 | I/O | TB0 CCR3 capture: CCI3A input, compare: Out3 | |
TB0.3 | 80 | I/O | TB0 CCR3 capture: CCI3B input, compare: Out3 | |
TB0.4 | 12 | I/O | TB0 CCR4 capture: CCI4A input, compare: Out4 | |
TB0.4 | 36 | I/O | TB0 CCR4 capture: CCI4B input, compare: Out4 | |
TB0.5 | 13 | I/O | TB0 CCR5 capture: CCI5A input, compare: Out5 | |
TB0.5 | 37 | I/O | TB0CCR5 capture: CCI5B input, compare: Out5 | |
TB0.6 | 25 | I/O | TB0 CCR6 capture: CCI6B input, compare: Out6 | |
TB0.6 | 38 | I/O | TB0 CCR6 capture: CCI6A input, compare: Out6 | |
TB0CLK | 28, 50 | I | TB0 clock input | |
TB0OUTH | 24, 35, 80, 84 | I | Switch all PWM outputs high impedance input – TB0 | |
UART | UCA0RXD | 17, 48 | I | Receive data for eUSCI_A0 UART mode |
UCA0TXD | 16, 47 | O | Transmit data for eUSCI_A0 UART mode | |
UCA1RXD | 19 | I | Receive data for eUSCI_A1 UART mode | |
UCA1TXD | 18 | O | Transmit data for eUSCI_A1 UART mode | |
UCA2RXD | 68, 55 | I | Receive data for eUSCI_A2 UART mode | |
UCA2TXD | 67, 54 | O | Transmit data for eUSCI_A2 UART mode | |
UCA3RXD | 81 | I | Receive data for eUSCI_A3 UART mode | |
UCA3TXD | 82 | O | Transmit data for eUSCI_A3 UART mode | |
USS | USSTRG | 15 | I | USS trigger |
USSXTIN | 97 | I | Input for crystal or resonator of oscillator USSXT | |
USSXTOUT | 98 | O | Output for crystal or resonator of oscillator USSXT | |
USSXT_BOUT | 95 | O | Buffered output clock of USSXT | |
CH0_IN | 91 | I | USS channel 0 RX | |
CH0_OUT | 90 | I/O | USS channel 0 TX | |
CH1_IN | 85 | I | USS channel 1 RX | |
CH1_OUT | 86 | I/O | USS channel 1 TX |