JAJSG23E January   2015  – August 2018 MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics - Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM2, LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    10. 5.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 5.11 Typical Characteristics, Current Consumption per Module
    12. 5.12 Thermal Resistance Characteristics
    13. 5.13 Timing and Switching Characteristics
      1. 5.13.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.13.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.13.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.13.4  Wake-up Characteristics
        1. Table 5-9  Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charge
        3. 5.13.4.1   Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.13.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.13.5.1   Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        4. Table 5-13 Pin-Oscillator Frequency, Ports Px
        5. 5.13.5.2   Typical Characteristics, Pin-Oscillator Frequency
      6. 5.13.6  Timer_A and Timer_B
        1. Table 5-14 Timer_A
        2. Table 5-15 Timer_B
      7. 5.13.7  eUSCI
        1. Table 5-16 eUSCI (UART Mode) Clock Frequency
        2. Table 5-17 eUSCI (UART Mode)
        3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-19 eUSCI (SPI Master Mode)
        5. Table 5-20 eUSCI (SPI Slave Mode)
        6. Table 5-21 eUSCI (I2C Mode)
      8. 5.13.8  Segment LCD Controller
        1. Table 5-22 LCD_C Recommended Operating Conditions
        2. Table 5-23 LCD_C Electrical Characteristics
      9. 5.13.9  ADC12
        1. Table 5-24 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-25 12-Bit ADC, Timing Parameters
        3. Table 5-26 12-Bit ADC, Linearity Parameters With External Reference
        4. Table 5-27 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
        5. Table 5-28 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
        6. Table 5-29 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
        7. Table 5-30 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
        8. Table 5-31 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
        9. Table 5-32 12-Bit ADC, Temperature Sensor and Built-In V1/2
        10. Table 5-33 12-Bit ADC, External Reference
      10. 5.13.10 REF Module
        1. Table 5-34 REF, Built-In Reference
      11. 5.13.11 Comparator
        1. Table 5-35 Comparator_E
      12. 5.13.12 FRAM Controller
        1. Table 5-36 FRAM
      13. 5.13.13 Emulation and Debug
        1. Table 5-37 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
      1. 6.3.1 Peripherals in Low-Power Modes
      2. 6.3.2 Idle Currents of Peripherals in LPM3 and LPM4
    4. 6.4  Interrupt Vector Table and Signatures
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  FRAM
    8. 6.8  RAM
    9. 6.9  Tiny RAM
    10. 6.10 Memory Protection Unit (MPU) Including IP Encapsulation
    11. 6.11 Peripherals
      1. 6.11.1  Digital I/O
      2. 6.11.2  Oscillator and Clock System (CS)
      3. 6.11.3  Power-Management Module (PMM)
      4. 6.11.4  Hardware Multiplier
      5. 6.11.5  Real-Time Clock (RTC_C)
      6. 6.11.6  Watchdog Timer (WDT_A)
      7. 6.11.7  System Module (SYS)
      8. 6.11.8  DMA Controller
      9. 6.11.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.11.10 Timer_A TA0, Timer_A TA1
      11. 6.11.11 Timer_A TA2
      12. 6.11.12 Timer_A TA3
      13. 6.11.13 Timer_B TB0
      14. 6.11.14 ADC12_B
      15. 6.11.15 Comparator_E
      16. 6.11.16 CRC16
      17. 6.11.17 CRC32
      18. 6.11.18 AES256 Accelerator
      19. 6.11.19 True Random Seed
      20. 6.11.20 Shared Reference (REF_A)
      21. 6.11.21 LCD_C
      22. 6.11.22 Embedded Emulation
        1. 6.11.22.1 Embedded Emulation Module (EEM)
        2. 6.11.22.2 EnergyTrace++ Technology
      23. 6.11.23 Input/Output Diagrams
        1. 6.11.23.1  Digital I/O Functionality Port P1 to P7 and P9
        2. 6.11.23.2  Capacitive Touch Functionality on Port P1 to P7, P9, and PJ
        3. 6.11.23.3  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger
        4. 6.11.23.4  Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger
        5. 6.11.23.5  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
        6. 6.11.23.6  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
        7. 6.11.23.7  Port P4 (P4.2 to P4.7) Input/Output With Schmitt Trigger
        8. 6.11.23.8  Port P5 (P5.4 to P5.7) Input/Output With Schmitt Trigger
        9. 6.11.23.9  Port P6 (P6.0 to P6.6) Input/Output With Schmitt Trigger
        10. 6.11.23.10 Port P7 (P7.0 to P7.4) Input/Output With Schmitt Trigger
        11. 6.11.23.11 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
        12. 6.11.23.12 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
        13. 6.11.23.13 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
        14. 6.11.23.14 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
    13. 6.13 Memory
      1. 6.13.1 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
      2. 7.2.2 LCD_C Peripheral
        1. 7.2.2.1 Partial Schematic
        2. 7.2.2.2 Design Requirements
        3. 7.2.2.3 Detailed Design Procedure
        4. 7.2.2.4 Layout Guidelines
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  使い始めと次の手順
    2. 8.2  デバイスの項目表記
    3. 8.3  ツールとソフトウェア
    4. 8.4  ドキュメントのサポート
    5. 8.5  関連リンク
    6. 8.6  Community Resources
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

Table 5-5 High-Frequency Crystal Oscillator, HFXT(5)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IDVCC.HFXT HFXT oscillator crystal current HF mode at typical ESR fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1(8),
TA = 25°C,
CL,eff = 18 pF, typical ESR, Cshunt 		3.0 V 75 μA
fOSC = 8 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 1
TA = 25°C,
CL,eff = 18 pF, typical ESR, Cshunt 		120
fOSC = 16 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 2, HFFREQ = 2,
TA = 25°C,
CL,eff = 18 pF, typical ESR, Cshunt 		190
fOSC = 24 MHz
HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3,
TA = 25°C,
CL,eff = 18 pF, typical ESR, Cshunt 		250
fHFXT HFXT oscillator crystal frequency, crystal mode HFXTBYPASS = 0, HFFREQ = 1 (8)(7) 4 8 MHz
HFXTBYPASS = 0, HFFREQ = 2 (7) 8.01 16
HFXTBYPASS = 0, HFFREQ = 3 (7) 16.01 24
DCHFXT HFXT oscillator duty cycle Measured at SMCLK,
fHFXT = 16 MHz		 40% 50% 60%
fHFXT,SW HFXT oscillator logic-level square-wave input frequency, bypass mode HFXTBYPASS = 1, HFFREQ = 0(6)(7) 0.9 4 MHz
HFXTBYPASS = 1, HFFREQ = 1(6)(7) 4.01 8
HFXTBYPASS = 1, HFFREQ = 2(6)(7) 8.01 16
HFXTBYPASS = 1, HFFREQ = 3(6)(7) 16.01 24
DCHFXT, SW HFXT oscillator logic-level square-wave input duty cycle HFXTBYPASS = 1 40% 60%
OAHFXT Oscillation allowance for HFXT crystals(9) HFXTBYPASS = 0,
HFXTDRIVE = 0, HFFREQ = 1(8),
fHFXT,HF = 4 MHz, CL,eff = 16 pF		 450 Ω
HFXTBYPASS = 0,
HFXTDRIVE = 1, HFFREQ = 1,
fHFXT,HF = 8 MHz, CL,eff = 16 pF		 320
HFXTBYPASS = 0,
HFXTDRIVE = 2, HFFREQ = 2,
fHFXT,HF = 16 MHz, CL,eff = 16 pF		 200
HFXTBYPASS = 0,
HFXTDRIVE = 3, HFFREQ = 3,
fHFXT,HF = 24 MHz, CL,eff = 16 pF		 200
tSTART,HFXT Start-up time(10) fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1,
TA = 25°C, CL,eff = 16 pF		 3.0 V 1.6 ms
fOSC = 24 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3,
TA = 25°C, CL,eff = 16 pF		 3.0 V 0.6
CHFXIN Integrated load capacitance at HFXIN terminaI(1)(2) 2 pF
CHFXOUT Integrated load capacitance at HFXOUT terminaI(1)(2) 2 pF
fFault,HFXT Oscillator fault frequency(4)(3) 0 800 kHz
(1) This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN and COUT is the total capacitance at the HFXIN and HFXOUT terminals, respectively.
(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance of the selected crystal is met.
(3) Measured with logic-level input frequency but also applies to operation with crystals.
(4) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. A static condition or stuck at fault condition will set the flag.
(5) To improve EMI on the HFXT oscillator the following guidelines should be observed.
  • Keep the traces between the device and the crystal as short as possible.
  • Design a good ground plane around the oscillator pins.
  • Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.
  • Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.
  • Use assembly materials and processes that avoid any parasitic load on the oscillator HFXIN and HFXOUT pins.
  • If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(6) When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCHFXT, SW.
(7) Maximum frequency of operation of the entire device cannot be exceeded.
(8) HFFREQ = {0} is not supported for HFXT crystal mode of operation.
(9) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(10) Includes start-up counter of 1024 clock cycles.

Table 5-6 lists the characteristics of the DCO.